US2002158325A1PendingUtilityA1

Semiconductor device and manufacturing method thereof

Assignee: SHARP KKPriority: Feb 17, 1999Filed: Jun 6, 2002Published: Oct 31, 2002
Est. expiryFeb 17, 2019(expired)· nominal 20-yr term from priority
A63B 60/06A63B 53/14A63B 53/08A63B 2102/32H10W 90/754H10W 90/753H10W 90/752H10W 90/734H10W 90/732H10W 90/20H10W 74/00H10W 72/07553H10W 72/07532H10W 72/07521H10W 72/07511H10W 72/07141H10W 72/5525H10W 72/5524H10W 72/5522H10W 72/5473H10W 72/5434H10W 72/5366H10W 72/5363H10W 72/01551H10W 72/952H10W 72/932H10W 72/884H10W 72/547H10W 72/537H10W 72/536H10W 72/531H10W 72/075H10W 72/59H10W 90/00
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Claims

Abstract

In a manufacturing method of a semiconductor device, a substrate and a plurality of semiconductor chips stacked on the substrate are connected to each other by a ball bonding method adopting a reverse method. Specifically, after first bonding on a bonding pad on the substrate, a gold wire is led to a bonding pad of a semiconductor chip of the bottom layer, and by second bonding, a wire for connecting the substrate and the semiconductor chip of the bottom layer is formed. Similarly, other semiconductor chips are also connected to the substrate from the layer on the bottom. As a result, it is possible to reduce the package size, to provide a sufficient clearance between wires, and to reduce restrictions on combinations of semiconductor chips to be stacked.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A method for manufacturing a semiconductor device in which semiconductor chips are stacked on a substrate, said method comprising in a step of connecting the substrate and the semiconductor chips by wire bonding by a ball bonding method the step of: 
 first bonding a wire on a bonding pad on a lower layer of two different layers of multiple layers composed of the substrate and the semiconductor chips and thereafter second bonding the wire on a bonding pad on an upper layer of the two different layers so as to connect the two different layers to each other.    
     
     
         2 . The method as set forth in  claim 1 , comprising the step of first bonding a wire on a bonding pad on the upper layer of the two different layers of the multiple layers composed of the substrate and the semiconductor chips and thereafter second bonding the wire on a bonding pad on the lower layer of the two different layers so as to connect the two different layers to each other.  
     
     
         3 . The method as set forth in  claim 1 , comprising the steps of: 
 first bonding a wire on a bonding pad of the substrate and thereafter second bonding the wire on a bonding pad on a semiconductor chip adjacently on the substrate so as to connect the substrate and the semiconductor chip to each other; and    first bonding a wire on a bonding pad on the substrate and thereafter second bonding the wire on a bonding pad on other semiconductor chips so as to connect the substrate and the other semiconductor chips to each other.    
     
     
         4 . The method as set forth in  claim 2 , comprising the steps of: 
 first bonding a wire on a bonding pad on a semiconductor chip adjacently on the substrate and thereafter second bonding the wire on a bonding pad of the substrate so as to connect the substrate and the semiconductor chip to each other; and    first bonding a wire on a bonding pad on the substrate and thereafter second bonding the wire on a bonding pad on other semiconductor chips so as to connect the substrate and the other semiconductor chips to each other.    
     
     
         5 . The method as set forth in  claim 2 , comprising in a step of connecting to one another three different layers of the multiple-layers composed of the substrate and the semiconductor chips by wire bonding using a bonding pad of a middle layer as a common bonding pad the steps of: 
 first bonding a wire on a bonding pad on a bottom layer of the three different layers and thereafter second bonding the wire on the bonding pad on the middle layer so as to connect the bottom layer and the middle layer to each other; and    first bonding a wire on a bonding pad on a top layer of the three different layers and thereafter second bonding the wire on the bonding pad on the middle layer so as to connect the top layer and the middle layer to each other.    
     
     
         6 . The method as set forth in  claim 5 , comprising the steps of: 
 forming a bump on the bonding pad on the middle layer; and    carrying out the second bonding on the bump.    
     
     
         7 . The method as set forth in  claim 2 , comprising in a step of connecting to one another three different layers of the multiple-layers composed of the substrate and the semiconductor chips by wire bonding using a bonding pad of a middle layer as a common bonding pad the steps of: 
 first bonding a wire on a bonding pad on a top layer of the three different layers and thereafter second bonding the wire on the bonding pad of the middle layer so as to connect the top layer and the middle layer to each other; and    first bonding a wire on the bonding pad on the middle layer of the three different layers and thereafter second bonding the wire on a bonding pad on a bottom layer of the three different layers so as to connect the middle layer and the bottom layer to each other.    
     
     
         8 . The method as set forth in  claim 7 , comprising the steps of: 
 forming a bump on the bonding pad on the middle layer;    carrying out the second bonding of the wire for connecting the top layer and the middle layer to each other on the bump; and    carrying out the first bonding of the wire for connecting the middle layer and the bottom layer to each other on the bump.    
     
     
         9 . The method as set forth in  claim 1 , comprising in a step of connecting to one another three different layers of the multiple-layers composed of the substrate and the semiconductor chips by wire bonding using a bonding pad of a middle layer as a common bonding pad the steps of: 
 first bonding a wire on a bonding pad on a bottom layer of the three different layers and thereafter second bonding the wire on the bonding pad of the middle layer so as to connect the bottom layer and the middle layer to each other; and    first bonding a wire on the bonding pad on the middle layer of the three different layers and thereafter second bonding the wire on a bonding pad on a top layer of the three different layers so as to connect the middle layer and the top layer to each other.    
     
     
         10 . The method as set forth in  claim 9 , comprising the steps of: 
 forming a bump on the bonding pad of the middle layer;    carrying out the second bonding of the wire for connecting the bottom layer and the middle layer to each other on the bump; and    carrying out the first bonding of the wire for connecting the middle layer and the top layer to each other on the bump.    
     
     
         11 . The method as set forth in  claim 1 , wherein the lower layer is the substrate.  
     
     
         12 . The method as set forth in  claim 1 , wherein the semiconductor chips are stacked in two layers on the substrate.  
     
     
         13 . The method as set forth in  claim 1 , wherein the semiconductor chips are stacked in three layers on the substrate.  
     
     
         14 . The method as set forth in  claim 1 , further comprising in the second bonding of the wire on the bonding pad on a semiconductor chip of the upper layer the step of forming a bump on the bonding pad.  
     
     
         15 . The method as set forth in  claim 14 , further comprising the step of crushing the bump on the bonding pad.  
     
     
         16 . A semiconductor device in which a substrate and semiconductor chips stacked on the substrate are connected to one another by wire bonding by a ball bonding method, 
 wherein two different layers of multiple-layers composed of the substrate and the semiconductor chips are connected to each other by first bonding a wire on a bonding pad on a lower layer of the two different layers and thereafter by second bonding the wire on a bonding pad on an upper layer of the two different layers.    
     
     
         17 . The semiconductor device as set forth in  claim 16 , 
 wherein two different layers of multiple-layers composed of the substrate and the semiconductor chips are connected to each other by first bonding a wire on a bonding pad on an upper layer of the two different layers and thereafter by second bonding the wire on a bonding pad on a lower layer of the two different layers.    
     
     
         18 . The semiconductor device as set forth in  claim 16 , wherein the substrate and a semiconductor chip adjacently on the substrate are connected to each other by first bonding a wire on a bonding pad on the substrate and thereafter by second bonding the wire on a bonding pad on the semiconductor chip, and 
 the substrate and other semiconductor chips are connected to each other by first bonding a wire on a bonding chip on the substrate and thereafter second bonding the wire on a bonding pad of the other semiconductor chips.    
     
     
         19 . The semiconductor device as set forth in  claim 17 , wherein the substrate and a semiconductor chip adjacently on the substrate are connected to each other by first bonding a wire on a bonding pad on the semiconductor chip and thereafter by second bonding the wire on a bonding pad on the substrate, and 
 the substrate and other semiconductor chips are connected to each other by first bonding a wire on a bonding pad on the substrate and thereafter by second bonding the wire on a bonding pad of the other semiconductor chips.    
     
     
         20 . The semiconductor device as set forth in  claim 17 , wherein three different layers of the multiple-layers composed of the substrate and the semiconductor chips are connected to one another by wire bonding using a bonding pad of a middle layer as a common bonding pad, 
 a bottom layer and the middle layer of the three different layers being connected to each other by first bonding a wire on a bonding pad on the bottom layer and by second bonding the wire on the bonding pad on the middle layer, and    a top layer and the middle layer of the three different layers being connected to each other by first bonding a wire on a bonding pad on the top layer and thereafter by second bonding the wire on the bonding pad on the middle layer.    
     
     
         21 . The semiconductor device as set forth in  claim 20 , wherein on the bonding pad on the middle layer is formed a bump to be used for the second bonding.  
     
     
         22 . The semiconductor device as set forth in  claim 17 , wherein three different layers of the multiple-layers composed of the substrate and the semiconductor chips are connected to one another by wire bonding using a bonding pad of a middle layer as a common bonding pad, 
 a top layer and the middle layer of the three different layers being connected to each other by first bonding a wire on a bonding pad on the top layer and thereafter by second bonding the wire on the bonding pad of the middle layer, and    the middle layer and a bottom layer of the three different layers being connected to each other by first bonding a wire on the bonding pad on the middle layer and thereafter by second bonding the wire on a bonding pad on the bottom layer.    
     
     
         23 . The semiconductor device as set forth in  claim 22 , wherein on the bonding pad of the middle layer is formed a bump to be used for the second bonding of the wire for connecting the top layer and the middle layer and to be used for the first bonding of the wire for connecting the middle layer and the bottom layer.  
     
     
         24 . The semiconductor device as set forth in  claim 16 , wherein three different layers of the multiple-layers composed of the substrate and the semiconductor chips are connected to one another by wire bonding using a bonding pad of a middle layer as a common bonding pad, 
 a bottom layer and the middle layer of the three different layers being connected to each other by first bonding a wire on a bonding pad on the bottom layer and thereafter by second bonding the wire on the bonding pad on the middle layer, and    the middle layer and a top layer of the three different layers being connected to each other by first bonding a wire on the bonding pad on the middle layer and thereafter second bonding the wire on a bonding pad on the top layer.    
     
     
         25 . The semiconductor device as set forth in  claim 24 , wherein on the bonding pad of the middle layer is formed a bump to be used for the second bonding of the wire for connecting the bottom layer and the middle layer and to be used for the first bonding of the wire for connecting the middle layer and the top layer.  
     
     
         26 . The semiconductor device as set forth in  claim 16 , wherein the lower layer is the substrate.  
     
     
         27 . The semiconductor device as set forth in  claim 16 , wherein the semiconductor chips are stacked in two layers on the substrate.  
     
     
         28 . The semiconductor device as set forth in  claim 16 , wherein the semiconductor chips are stacked in three layers on the substrate.  
     
     
         29 . The semiconductor device as set forth in  claim 16 , wherein on the bonding pad of a semiconductor chip of the upper layer is formed a bump.  
     
     
         30 . The semiconductor device as set forth in  claim 19 , wherein the bump is crushed on the bonding pad.  
     
     
         31 . The semiconductor device as set forth in  claim 16 , wherein layers of the substrate and the semiconductor chips are stacked such that positions of the bonding pads are aligned between adjacent upper and lower layers.  
     
     
         32 . The semiconductor device as set forth in  claim 16 , wherein the semiconductor chips are arranged such that the upper layer protrudes from the lower layer.  
     
     
         33 . The semiconductor device as set forth in  claim 16 , wherein the semiconductor device has a structure of a chip size package.

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