Flip chip interconnected structure and a fabrication method thereof

Abstract

A flip chip interconnected structure comprises a chip having an active surface in which a plurality of bonding pads are formed on the active surface of the chip. A substrate has a surface and a chip locating region. The chip locating region is on the surface of the substrate and a plurality of nodes are formed on the chip locating region. A plurality of solder balls are respectively connected to the bonding pads and the nodes. The solder balls have various sizes. The chip is bonded to the chip locating region of the substrate by the solder balls.

What is claimed is:  
     
         1 . A flip chip interconnected structure, comprising: 
 a substrate having a first surface, a chip locating region and a plurality of nodes, wherein the chip locating region is on the first surface of the substrate and the nodes are formed on the chip locating region;    a chip having an active surface on which a plurality of bonding pads are formed, the active surface of the chip corresponding to the first surface of the substrate; and    a plurality of solder balls, wherein each solder ball respectively connects to one of the bonding pads and one of the nodes, and sizes of the solder balls are varied to allow the chip to bond to the chip locating region of the substrate.    
     
     
         2 . The structure of  claim 1 , wherein the structure further comprises an encapsulating material filled in between the chip and the substrate, and encapsulating the solder balls.  
     
     
         3 . The structure of  claim 1 , wherein the solder balls are arranged in a matrix, and sizes of the solder balls located at a center region of the chip locating region are smaller than sizes of the solder balls located at a peripheral region of the chip locating region.  
     
     
         4 . The structure of  claim 1 , wherein each solder ball is made of a solder paste and a bump, wherein the solder paste covers the bump, and the bump is made of a tin/lead alloy containing a high percentage of lead.  
     
     
         5 . The structure of  claim 4 , wherein the bump is made of the tin/lead alloy with a ratio of 5/95, and the solder paste is made of a tin/lead alloy with a ratio of 63/37.  
     
     
         6 . The structure of  claim 4 , wherein a size of the solder paste located at a center region of the chip locating region is smaller than a size of the solder paste located at a peripheral region of the chip locating region.  
     
     
         7 . A flip chip interconnected structure, comprising: 
 a substrate having a first surface, a chip locating region and a plurality of nodes, wherein the chip locating region is on the first surface of the substrate and the nodes are formed on the chip locating region, and the chip locating region further comprises a solder mask layer having a plurality of solder mask openings, and the nodes are exposed by the solder mask openings, wherein sizes of the solder mask openings are varied;    a chip having an active surface and a plurality of bonding pads formed on the active surface, wherein the active surface of the chip corresponds to the first surface of the substrate; and    a plurality of solder balls, wherein each solder ball is respectively connected to one of the bonding pads and one of the nodes, wherein sizes of the solder balls are varied to allow the chip to bond to the chip locating region of the substrate.    
     
     
         8 . The structure of  claim 7 , wherein the flip chip interconnected structure further comprises an encapsulating material filled in between the chip and the substrate, and encapsulating the solder balls.  
     
     
         9 . The structure of  claim 7 , wherein sizes of the solder mask openings located at a center region of the chip locating region are larger than sizes of the solder mask openings located at a peripheral region of the chip locating region.  
     
     
         10 . A method of fabricating a flip chip interconnected structure, the steps of the method comprising: 
 providing a chip having an active surface, wherein a plurality of bonding pads are formed on the active surface, and a plurality of bumps are formed on the bonding pads;    providing a substrate having a first surface, wherein a chip locating region is on the first surface, and a plurality of nodes are formed on the chip locating region;    applying a solder paste to cover the nodes of the chip locating region, wherein the solder paste forms a plurality of solder structures with various sizes; and    performing a bonding process, wherein the active surface of the chip is bonded to the surface of the substrate by bonding the bumps to the solder structures, and a heating process is carried out to combine the bumps and the solder structures to form a plurality of solder balls, wherein each solder ball is bonded respectively to one of the bonding pads and one of the nodes, and the chip is bonded to the chip locating region of the substrate through the solder balls.    
     
     
         11 . The method of  claim 10 , wherein the bonding process further comprises an encapsulating process, wherein an encapsulating material is filled in between the chip and the substrate, and encapsulating the solder balls.  
     
     
         12 . The method of  claim 10 , wherein the step of applying the solder paste further comprises: 
 providing a stencil printing board having a plurality of openings, wherein the stencil printing board is located on the substrate and the nodes of the chip locating region are exposed by the openings;    filling the openings with the solder paste by a screen printing method;    forming solder structures with various sizes according to different sizes of the openings and positions of the solder structures corresponding to positions of the nodes.    
     
     
         13 . The method of  claim 12 , wherein the openings are arranged in a matrix, and sizes of the openings located at a peripheral region of the stencil printing board are larger than sizes of the openings near a center region of the stencil printing board, thereby the amount of the solder paste filled in the opening at the peripheral region is more than the amount of the solder paste filled in the openings at the center region.  
     
     
         14 . The method of  claim 10 , wherein the bonding process further comprises a reflow method to combine the bumps and the solder structures.  
     
     
         15 . The method of  claim 10 , wherein the solder balls are arranged in a matrix, and sizes of the solder balls located at a center region of the chip locating region are smaller than sizes of the solder balls located at a peripheral region of the chip locating region.  
     
     
         16 . The method of  claim 10 , wherein each solder ball is made of a tin/lead alloy containing a high percentage of lead.  
     
     
         17 . A method of fabricating a flip chip interconnected structure, the steps of the method comprising: 
 providing a chip having an active surface, wherein a plurality of bonding pads are formed on the active surface, and a plurality of bumps are formed on the bonding pads;    providing a substrate having a first surface, wherein a chip locating region is on the first surface, and a solder mask layer and a plurality of nodes are formed on the chip locating region, wherein a plurality of solder mask openings having various sizes are formed on the solder mask layer, and the nodes are exposed by the solder mask openings;    applying a solder paste to cover the node of the chip locating region; and    performing a bonding process, wherein the active surface of the chip is bonded to the surface of the substrate by bonding the bumps to the solder paste, and a heating process is carried out to combine each bump and each solder paste to form a solder ball, wherein a plurality of solder balls are formed and are bonded respectively to one of the bonding pads and one of the nodes, and the chip is bonded to the chip locating region of the substrate through the solder balls.    
     
     
         18 . The method of  claim 17 , wherein the bonding process further comprises an encapsulating process, wherein an encapsulating material is filled in between the chip and the substrate, and encapsulating the solder balls.  
     
     
         19 . The method of  claim 17 , wherein sizes of the solder mask openings located at a center region of the chip locating region are larger than sizes of the solder mask openings located at a peripheral region of the chip locating region.  
     
     
         20 . The method of  claim 17 , wherein the bonding process further comprises a reflow method to combine the bumps and the solder structures.