Method for forming interconnect structure with low dielectric constant

Abstract

The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.

What is claimed is:  
     
         1 . A method for forming low dielectric constant inter-metal dielectric layer, said method comprising: 
 providing a semiconductor substrate;    forming a first dielectric layer on said semiconductor substrate;    forming a plurality of conductor structures in said first dielectric layer;    removing partial said first dielectric layer, said removing step using said conductor structures as etch mask; and    forming a second dielectric layer between said conductor structure, said second dielectric layer having a dielectric constant smaller than said first dielectric layer having.    
     
     
         2 . The method according to  claim 1 , wherein said a etch mask is a self-aligned hard mask.  
     
     
         3 . The method according to  claim 1 , wherein said first dielectric layer can be made of oxide-based material.  
     
     
         4 . The method according to  claim 1 , wherein said second dielectric layer can be made of spin-on dielectric material.  
     
     
         5 . A method for improving mechanical strength of a low dielectric constant inter-metal dielectric layer, said method comprising: 
 providing a semiconductor substrate;    forming an oxide-based inter-metal dielectric layer on said semiconductor substrate;    forming a plurality of metal structures in said oxide-based inter-metal dielectric layer;    removing partial said oxide-based inter-metal dielectric layer, said removing step using said metal structures as an etch mask; and    spinning a dielectric layer between said metal structures, said dielectric layer having a dielectric constant smaller than said oxide-based inter-metal dielectric layer having.    
     
     
         6 . The method according to  claim 5 , wherein said etch mask is a self-aligned hard mask.  
     
     
         7 . The method according to  claim 5 , wherein said oxide-based inter-metal dielectric layer comprises an undoped silicate glass layer.  
     
     
         8 . A semiconductor structure with low dielectric constant intermetal dielectric, said semiconductor structure comprising: 
 a substrate;    a first dielectric layer on said substrate;    a plurality of conductor structures in said first dielectric layer; and    a plurality of second dielectric structures in said first dielectric layer and between said conductor structures, each said second dielectric structure having a dielectric constant smaller than said first dielectric layer having.    
     
     
         9 . The semiconductor structure of  claim 8 , wherein said second dielectric structures comprises made of spin-on dielectric material.  
     
     
         10 . The semiconductor structure of  claim 8 , wherein said first dielectric layer comprises an oxide-based dielectric layer.  
     
     
         11 . The semiconductor structure of  claim 8 , wherein said second dielectric structures are adjacent to said conductor structures.  
     
     
         12 . The semiconductor structure of  claim 8 , wherein said conductor structures comprise a contact structure made of metal material.  
     
     
         13 . A semiconductor structure with low dielectric constant inter-metal dielectric, said semiconductor structure comprising: 
 a substrate;    a first dielectric layer on said substrate;    a plurality of metal structures in said first dielectric layer; and    a plurality of spin-on dielectric structures in said first dielectric layer and between said metal structures, each said spin-on dielectric structure having a dielectric constant smaller than said first dielectric layer having.    
     
     
         14 . The semiconductor structure of  claim 13 , wherein said spin-on structures are adjacent to said metal structures and said first dielectric layer.  
     
     
         15 . The semiconductor structure of  claim 13 , wherein said spin-on dielectric structures are adjacent to said substrate.