Method and structure for retarding high temperature agglomeration of silicides using alloys

Abstract

Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial metal layer used in forming the silicide.

What is claimed is:  
     
         1 . A method of fabricating a substantially non-agglomerated metal alloy silicide contact comprising the steps of: 
 (a) forming a metal alloy layer over a portion of a silicon-containing substrate, wherein said metal alloy layer comprises Co or Ti and an alloying additive, said silicon-containing layer not containing activated source/drain regions embedded therein;    (b) annealing said metal alloy layer at a temperature which is effective in converting a portion of said metal alloy layer into a metal alloy silicide layer, said metal alloy silicide layer being difficult to etch compared to said metal alloy layer;    (c) removing any remaining metal alloy layer not converted in step (b);    (d) optionally performing a second anneal that is carried out at a temperature that is effective in converting the metal alloy silicide layer formed in step (b) to its lowest resistance phase; and    (e) forming activated said source/drain regions in said silicon-containing substrate by at least annealing at a temperature of about 900° C. or above, whereby the metal alloy silicide layer does not agglomerate during said activation annealing and it is in its lowest resistance phase after said activation annealing    
     
     
         2 . The method of  claim 1  further comprising pre-annealing the metal alloy layer prior to step (b) at a temperature sufficient to form a metal rich alloy silicide layer.  
     
     
         3 . The method of  claim 1  further comprising forming an optional barrier layer over said metal alloy layer prior to step (b), wherein said optional barrier layer is removed by step (c).  
     
     
         4 . The method of  claim 1  wherein said alloying additive is C, Al, Si, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Ge, Y, Zr, Nb, Mo, Ru, Rh, Pd, In, Sn, La, Hf, Ta, W, Re, Ir, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu or mixtures thereof.  
     
     
         5 . The method of  claim 4  wherein said alloying additive is C, Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Ge, Y, Zr, Nb, Mo, Ru, Rh, Pd, In, Sn, La, Hf, Ta, W, Re, Ir or mixtures thereof.  
     
     
         6 . The method of  claim 5  wherein said alloying additive is Ti, V, Cr, Ge, Nb, Rh, Ta, W, Hf, Zr, Mo, Re, Ir or mixtures thereof.  
     
     
         7 . The method of  claim 1  wherein said alloying additive is present is said metal alloy layer in an amount of from about 0.01 to about 50 atomic %.  
     
     
         8 . The method of  claim 7  wherein said alloying additive is present is said metal alloy layer in an amount of from about 0.1 to about 20 atomic %.  
     
     
         9 . The method of  claim 1  wherein said metal alloy layer comprises a Co alloy and step (b) forms a Co alloy monosilicide phase.  
     
     
         10 . The method of  claim 3  wherein said optional oxygen barrier layer is composed of TiN.  
     
     
         11 . The method of  claim 1  wherein said silicon-containing substrate comprises a single crystal Si, polycrystalline Si, SiGe, amorphous Si, or a silicon-on-insulator (SOI).  
     
     
         12 . The method of  claim 2  wherein said pre-annealing step is carried out using rapid thermal annealing (RTA).  
     
     
         13 . The method of  claim 12  wherein said RTA is carried out at a temperature of from about 350° to about 450° C. for a time period of about 300 seconds or less.  
     
     
         14 . The method of  claim 1  wherein said annealing step (b) is carried out by RTA.  
     
     
         15 . The method of  claim 14  wherein said RTA is carried out at a temperature of from about 400° to about 700° C. for a time period of about 300 seconds or less.  
     
     
         16 . The method of  claim 1  wherein said optional annealing step is carried out by RTA.  
     
     
         17 . The method of  claim 16  wherein said RTA is carried out at a temperature of from about 700° to about 900° C. for a time period of about 300 seconds or less.  
     
     
         18 . The method of  claim 1  wherein said remaining metal alloy layer is removed utilizing a wet etch step that includes the use of an etchant that is selective for removing said layers.  
     
     
         19 . The method of  claim 1  wherein said low resistance phase of said metal alloy silicide layer is Co disilicide or C54 phase of TiSi 2 .  
     
     
         20 . The method of  claim 1  wherein said metal alloy layer is formed by a deposition process selected from the group consisting of chemical vapor deposition (CVD), plasma-assisted CVD, evaporation and sputtering.  
     
     
         21 . The method of  claim 1  wherein said metal alloy layer is formed by first depositing said metal and thereafter doping the deposited metal with said alloying additive.  
     
     
         22 . An electrical contact to a region of a silicon-containing substrate comprising: 
 a substrate having an exposed region of a silicon-containing semiconductor material, said silicon-containing semiconductor material having source/drain regions formed therein; and    a substantially non-agglomerated metal alloy silicide contact formed on a portion of said silicon-containing semiconductor substrate, wherein said substantially non-agglomerated metal alloy silicide contact withstands high temperature annealing conditions which are employed in fabricating the source/drain regions and is in its lowest resistance phase, said source/drain regions being formed after the metal alloy silicide contact.    
     
     
         23 . The electrical contact of  claim 22  wherein said alloying additive is C, Al, Si, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Ge, Y, Zr, Nb, Mo, Ru, Rh, Pd, In, Sn, La, Hf, Ta, W, Re, Ir, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu or mixtures thereof.  
     
     
         24 . The electrical contact of  claim 23  wherein said alloying additive is C, Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Ge, Y, Zr, Nb, Mo, Ru, Rh, Pd, In, Sn, La, Hf, Ta, W, Re, Ir or mixtures thereof.  
     
     
         25 . The electrical contact of  claim 24  wherein said alloying additive is Ti, V, Cr, Ge, Nb, Rh, Ta, W, Hf, Zr, Mo, Re, Ir or mixtures thereof  
     
     
         26 . The electrical contact of  claim 22  wherein said alloying additive is present in said first layer in an amount of from about 0.01 to about 50 atomic %.  
     
     
         27 . The electrical contact of  claim 22  wherein said low resistance phase of said metal alloy silicide layer is Co disilicide or C54 phase of TiSi 2 .