Mixed mode transceiver digital control network and collision-free communication method

Abstract

A mixed mode transceiver digital control network system is disclosed as including at least two nodes/transceivers connected with a DC power source and a cored inductor via a bus, in which each transceiver includes a current mode transmitter and a voltage mode receiver. A bi-directional voltage clamp is connected in parallel to the cored inductor. Electric current from the DC power source flows through the cored inductor and the bi-directional clamp into the bus. By reason of the flow of the electric current through the voltage clamp, a electric voltage pulse is generated and transmitted into the bus. The electric voltage pulse so transmitted into the bus is received by the voltage mode receiver and subsequently inputted into a micro-controller or processor of the node. There is also disclosed a method of setting one of a plurality of priority levels to each node forming the system, so that a node to which a higher priority level has a higher chance of transmitting its data packets. There is further disclosed a method of avoiding collision when two or more nodes/transceivers transmit their respective data packets at the same time.

What is claimed is:  
     
         1 . A digital data communication network system including a power supply means and at least two nodes, wherein said power supply means and said nodes are connected to one another via a transmission media whereby digital signals/data are transmissible between said nodes, wherein said power supply means supplies electric power to said nodes, and wherein at least one of said nodes includes a current mode transmitter and at least one of said nodes includes a voltage mode receiver.  
     
     
         2 . The system according to  claim 1  wherein at least one of said plurality of nodes includes a current mode transmitter and a voltage mode receiver.  
     
     
         3 . The system according to  claim 2  wherein a plurality of said nodes include a current mode transmitter and a voltage mode receiver.  
     
     
         4 . The system according to  claim 3  wherein each of said nodes includes a current mode transmitter and a voltage mode receiver.  
     
     
         5 . The system according to  claim 1  wherein said transmission media is a unshielded twisted pair wire.  
     
     
         6 . The system according to  claim 1  wherein said system includes pulse generating means through which electric current from said power supply means passes to induce a voltage pulse.  
     
     
         7 . The system according to  claim 6  wherein said pulse generating means comprises a current to voltage converter means.  
     
     
         8 . The system according to  claim 6  wherein said pulse generating means is connected in parallel to a current controller.  
     
     
         9 . The system according to  claim 1  wherein said power supply means comprises a DC power source.  
     
     
         10 . The system according to  claim 1  wherein said voltage mode receiver includes a capacitor and an inverter means.  
     
     
         11 . A digital data communication system for delivering digital signals from a current mode transmitter to a voltage mode receiver, said system including: 
 an electrically conductive cable coupling said transmitter and said receiver with each other, thereby providing a digital data communications path;    DC power supply means for producing a pre-determined electric potential, said power supply means having a first voltage terminal and a second voltage terminal;    current control means coupling said first voltage terminal of said power supply means to said cable for providing a first electric current path, said first electric current path operating as a low impedance path for DC current;    voltage control means connected in parallel with said current control means for controlling the voltage amplitude across said current control means, and for providing a second electrical path for transient electric current;    connecting means coupling said second voltage terminal of said power supply means to said cable to provide a power distribution path;    wherein said current mode transmitter is coupled to said cable for implementing a current loop, wherein said transmitter produces current pulses in said current loop to perform a current mode digital data transmission; and    wherein said voltage mode receiver is coupled to said cable for receiving voltage pulses on said cable produced by said voltage control means to perform a voltage mode digital data reception.    
     
     
         12 . The system according to  claim 11  wherein said conductive cable comprises a single twisted pair wire.  
     
     
         13 . The system according to  claim 11  wherein said current control means comprises a cored inductor.  
     
     
         14 . The system according to  claim 11  wherein said voltage control means comprises a bi-directional voltage clamp.  
     
     
         15 . The system according to  claim 11  wherein said pre-determined electric potential is substantially 24 volts.  
     
     
         16 . The system according to  claim 11  wherein each of said current mode transmitter and said voltage mode receiver includes: 
 a bridge rectifier having two terminals coupled to said cable for providing a non-polarity interface with said cable, said rectifier further including a +terminal and a −terminal;  
 a constant current source having a first current terminal and a second current terminal, wherein said first current terminal is coupled to said +terminal; and  
 a zener diode coupling said second current terminal of said constant current source to said −terminal of said rectifier to provide a power supply to said transmitter and said receiver.  
 
     
     
         17 . The system of  claim 16  wherein said transmitter further includes: 
 a transistor with a collector coupled to said +terminal of said rectifier, a base for inputting data to be transmitted into said transistor, and an emitter; and  
 a resistor coupling said emitter of said transistor and said −terminal of said rectifier for implementing a transmission output current loop.  
 
     
     
         18 . The system according to  claim 16  wherein said receiver includes an input capacitor for isolating the direct current potential on said +terminal of said bridge rectifier.  
     
     
         19 . A digital data communication network system for distributing power and for providing signal passing capabilities through a bus, said network including: 
 a plurality of nodes each including a mixed mode data bus transceiver for generating electric current pulses and receiving electric voltage pulses;    an electrically conductive cable coupling said nodes with one another to provide a path for power delivery and data communications;    a DC power supply means for producing a pre-determined electric potential, said power supply means having a first voltage terminal and a second voltage terminal;    current control means coupling said first voltage terminal of said power supply means to said cable for providing a first DC current low impedance path;    voltage control means connected in parallel with said current control means for controlling the voltage amplitude across said current control means and providing a second current path for transient current; and    connection means coupling said second voltage terminal of said power supply means to said conductive cable to provide a power distribution path.    
     
     
         20 . The system according to  claim 19  wherein said conductive cable comprises a single twisted pair wire.  
     
     
         21 . The system according to  claim 19  wherein said current control means includes a cored inductor.  
     
     
         22 . The system according to  claim 19  wherein said voltage control means includes a bi-directional voltage clamp.  
     
     
         23 . The system according to  claim 19  wherein said pre-determined electric potential is substantially 24 volts.  
     
     
         24 . The system according to  claim 19  wherein the frequency of said pulses is substantially between 5 kHz to 50 kHz.  
     
     
         25 . The system according to  claim 19  wherein each of said nodes includes a micro-controller/processor.  
     
     
         26 . The system according to  claim 19  wherein said data bus transceiver includes: 
 a bridge rectifier having a first and a second connection terminal for providing a non-polarity interface with said bus, said rectifier further including a +terminal and a −terminal;  
 a current mode transmitter coupled to said +terminal and said −terminal of said rectifier for implementing a current loop for producing electric current pulses to said bus to perform a current mode data transmission;  
 a voltage mode receiver coupled to said +terminal and said −terminal of said rectifier, said receiver receiving voltage pulses on said bus to perform a voltage mode data reception; and  
 current coupling means coupled to said +terminal and said −terminal of said rectifier for providing a regulated direct current supply to said transceiver.  
 
     
     
         27 . The system according to  claim 26  wherein said transceiver includes a transmitter including: 
 a transistor with a collector coupled to said +terminal of said rectifier, a base for inputting data to be transmitted to the transistor, and an emitter; and  
 a resistor having a first terminal coupled to said emitter of said transistor and a second terminal coupled to said −terminal of said rectifier.  
 
     
     
         28 . The system according to  claim 26  wherein said transceiver includes a receiver including: 
 a transistor with a collector coupled to said −terminal of said rectifier through a resistor for outputting the data received from said bus, and a base; and  
 a capacitor coupling said base of said transistor with said +terminal of said rectifier through a resistor for providing an AC path to said bus.  
 
     
     
         29 . The system according to  claim 26  wherein the current coupling means includes: 
 a constant current source having a first terminal and a second terminal, wherein said first terminal is coupled to said +terminal of said rectifier for sourcing a constant current; and  
 a zener diode coupling said second terminal of said constant current source and said −terminal of said rectifier for providing a regulated DC voltage source.  
 
     
     
         30 . A transceiver adapted to transmit and receive digital signals on a data bus which delivers direct current power and digital data simultaneously, said transceiver including: 
 a bridge rectifier having two connection terminals adapted to provide a non-polarity interface with said bus, said rectifier further including a +terminal and a −terminal;    a current mode transmitter coupled to said +terminal and said −terminal of said rectifier for implementing a current loop adapted to produce electric current pulses to said data bus to perform current mode data transmission;    a voltage mode receiver coupled to said +terminal and said −terminal of said rectifier, said receiver being adapted to receive electric voltage pulses on said data bus to perform voltage mode data reception; and    a current coupling means coupled to said +terminal and said −terminal of said rectifier, said current coupling means being adapted to provide a regulated direct current supply to said transmitter and said receiver and other means in said transceiver.    
     
     
         31 . The transceiver according to  claim 30  wherein said transmitter includes: 
 a transistor with a collector coupled to said +terminal of said rectifier and a base for inputting the data to be transmitted, and an emitter; and  
 a resistor having a first terminal coupled to said emitter of said transistor and a second terminal coupled to said −terminal of said rectifier.  
 
     
     
         32 . The transceiver according to  claim 30  wherein said receiver includes: 
 a transistor with a collector coupled to said −terminal of said rectifier through a resistor for outputting the data received, and a base; and  
 a capacitor coupled with said base of said transistor and said +terminal of said rectifier through a resistor, and being adapted to provide an AC path to said bus.  
 
     
     
         33 . The transceiver according to  claim 30  wherein said current coupling means includes: 
 a constant current source having a first terminal and a second terminal, wherein said first terminal is coupled with said +terminal of said rectifier and adapted for sourcing a constant current; and  
 a zener diode coupled with said second terminal of said constant current source and said −terminal of said rectifier, and adapted to provide a regulated DC electric voltage.  
 
     
     
         34 . The transceiver according to  claim 33  wherein the working voltage of said zener diode in said coupling means is substantially 5 volts.  
     
     
         35 . The transceiver according to  claim 30  wherein the pre-determined DC potential of said power is substantially 24 volts.  
     
     
         36 . The transceiver according to  claim 30  wherein the range of frequency of said current and voltage pulses in said transceiver is 5-50 kHz.  
     
     
         37 . The transceiver according to  claim 30  wherein said other means includes a micro-controller/processor.  
     
     
         38 . A method of communication in a mixed mode communication and control network system, wherein said system includes at least a first node, a second node, a power supply means, and current to voltage converter means connected with one another via a bus, comprising the steps of: 
 (a) generating at least a first electric pulse by said first node;    (b) transmitting said first electric pulse to said power supply means in the form of an electric current;    (c) causing a first electric current from said power supply means to pass through said current to voltage converter means to induce at least a second electric pulse; and    (d) transmitting said second electric pulse into said bus.    
     
     
         39 . The method according to  claim 38  wherein said first electric pulse is generated by a micro-controller/processor.  
     
     
         40 . The method according to  claim 39  wherein said first electric pulse is generated by said micro-controller/processor upon a change in state of an application module.  
     
     
         41 . The method according to  claim 38  wherein said current to voltage converter means is connected in parallel with a current control means.  
     
     
         42 . The method according to  claim 38  wherein a second electric current passes through said current control means when said first electric current passes through said current to voltage converter means.  
     
     
         43 . The method according to  claim 42  wherein the magnitude of said second electric current passing through said current control means varies at least in part in accordance with the period of time during which said second electric current passes through said current-control means.  
     
     
         44 . The method according to  claim 42  wherein the magnitude of said second electric current passing through said current control means depends at least in part on the electric voltage across said current control means.  
     
     
         45 . The method according to  claim 38  wherein the polarity of said first electric pulse is opposite to the polarity of the second electric pulse.  
     
     
         46 . The method according to  claim 38  wherein said second electric pulse is received by said second node.  
     
     
         47 . The method according to  claim 46  wherein said second node includes a voltage mode receiver for receiving said second electric pulse.  
     
     
         48 . The method according to  claim 47  wherein said voltage mode receiver of said second node includes inverter means for inverting the polarity of said second electric pulse.  
     
     
         49 . The method according to  claim 48  wherein said inverted second electric pulse is inputted into a micro-controller/processor of said second node.  
     
     
         50 . A method for medium access control in a mixed mode communication and control network system, wherein said system includes at least a first node and a second node each being adapted to transmit signals into a bus via which said nodes are connected with each other, including the steps of: 
 (a) establishing a plurality of priority levels each with a corresponding different range of waiting time;    (b) assigning one of said plurality of priority levels to each of said nodes;    (c) said first node generating a waiting time on the basis of the priority level assigned thereto;    (d) said first node checking whether said bus is free for transmission;    (e) said first node checking whether said waiting time has expired;    (f) repeating steps (d) and (e) until the waiting time has expired; and    (g) commencing transmission of a first data packet by said first node if said bus is free for transmission.    
     
     
         51 . The method according to  claim 50  wherein seven priority levels are established.  
     
     
         52 . The method according to  claim 50  wherein said period of waiting time comprises a pre-determined basic time component and a random time component.  
     
     
         53 . The method according to  claim 52  wherein the period of the basic time component of the waiting time of each priority level is different.  
     
     
         54 . The method according to  claim 52  wherein the period of the random time component of the waiting time of each priority level is set within a predetermined range.  
     
     
         55 . The method according to  claim 54  wherein the pre-determined range of period of the random time component of the waiting time of the priority levels is the same.  
     
     
         56 . The method according to  claim 52  wherein said random time component of the waiting time is generated by a micro-controller/processor of said first node.  
     
     
         57 . The method according to  claim 50  wherein said first node re-initialize the waiting time and starts from step (c) again if said bus is not free for transmission or not free for the full period of the waiting time.  
     
     
         58 . A method of transmitting data in a mixed mode communication and control network system, wherein said system includes at least a first node and a second node each being adapted to transmit pulses into a bus via which said nodes are connected with each other, including the steps of: 
 (a) said first node causing a pulse of a first polarity to be transmitted into said bus;    (b) said first node checking whether a pulse of said first polarity appears on said bus; and    (c) finishing sending said pulse of said first polarity into said bus for the full period of pulse time-width if a pulse of said first polarity is detected on said bus in step (b).    
     
     
         59 . The method according to  claim 58  wherein said first node stops sending said pulse of said first polarity into said bus if no pulse of said first polarity is detected on said bus in step (b).  
     
     
         60 . The method according to  claim 58  wherein said first polarity is positive.  
     
     
         61 . A method of transmitting at least one data packet for providing a collision-free communications in a mixed-mode multi-drop random access digital control network, wherein said network includes at least a first node and a second node each being adapted to transmit and receive data packets through a bus via which said nodes are connected with each other and constituting a wired-AND logic, wherein said data packet includes at least a logic high and a logic low to be transmitted into said bus, said method including the steps of: 
 (a) when said first node seeks to transmit said logic low into said bus, said first node: 
 (1) checks logic state from said bus;  
 (2) starts to transmit said logic low into said bus if said bus presents logic high in step (1) above;  
 (3) completes transmitting said logic low into said bus for the full period of the time-width of the said logic low; and  
   (b) when said first node seeks to transmit said logic high into said bus, said first node: 
 (1) starts to transmit said logic high into said bus;  
 (2) checks logic state from said bus;  
 (3) checks whether a pre-determined waiting time is up; and  
 (4) repeats steps (b)(2) and (b)(3) until said first node completes transmission of said logic high into said bus for the full period of the time-width of said logic high if said bus keep on presenting logic high in step (b)(2).  
   
     
     
         62 . The method according to  claim 61  wherein said first node stops transmission of said data packet and backs off if said bus does not present logic high in step (a)(1).  
     
     
         63 . The method according to  claim 61  wherein said first node stops transmission of said data packet and backs off if said bus does not present logic high in step (b)(2) for the full period of the time-width of said logic high.  
     
     
         64 . The method according to  claim 61  wherein all said steps are carried out by a micro-controller/processor of said first node.  
     
     
         65 . A method of transmitting at least one data packet for providing a collision-free communications in a mixed-mode multi-drop random access digital control network, wherein said network includes at least a first node and a second node each being adapted to transmit and receive data packets through a bus via which said nodes are connected with each other and constituting a wired-OR logic, wherein said data packet includes at least a logic high and a logic low to be transmitted into said bus, said method including the steps of: 
 (a) when said first node seeks to transmit said logic high into said bus, said first node: 
 (1) checks logic state from said bus;  
 (2) starts to transmit said logic high into said bus if said bus presents logic low in step (1) above;  
 (3) completes transmitting said logic high into said bus for the full period of the time-width of the said logic high; and  
   (b) when said first node seeks to transmit said logic low into said bus, said first node: 
 (1) starts to transmit said logic low into said bus;  
 (2) checks logic state from said bus;  
 (3) checks whether a pre-determined waiting time is up; and  
 (4) repeats steps (b)(2) and (b)(3) until said first node completes transmission of said logic low into said bus for the full period of the time-width of said logic low if said bus keep on presenting logic low in step (b)(2).  
   
     
     
         66 . The method according to  claim 65  wherein said first node stops transmission of said data packet and backs off if said bus does not present logic low in step (a)(1).  
     
     
         67 . The method according to  claim 65  wherein said first node stops transmission of said data packet and backs off if said bus does not present logic low in step (b)(2) for the full period of the time-width of said logic low.  
     
     
         68 . The method according to  claim 65  wherein all said steps are carried out by a micro-controller/processor of said first node.  
     
     
         69 . A transceiver adapted to transmit and receive digital signals/data via a mixed mode bus which delivers direct current power and digital data simultaneously, said transceiver including current mode transmitter means for implementing a current loop adapted to produce electric current pulses to said bus to perform a current mode data transmission, and voltage mode receiver means for receiving electric voltage pulses on said bus to perform voltage mode data reception.  
     
     
         70 . The transceiver according to  claim 69  wherein said transceiver further includes bridge rectifier means for providing a polarity insensitive interface with said bus.  
     
     
         71 . The transceiver according to  claim 69  wherein said transceiver further includes current coupling means for providing a regulated direct current source.  
     
     
         72 . The transceiver according to  claim 69  wherein said transmitter means comprises a sink current loop driver.  
     
     
         73 . The transceiver according to  claim 69  wherein said receiver means includes an input capacitor and an inverter means.  
     
     
         74 . The transceiver according to  claim 69  wherein said transceiver further includes a micro-controller/processor.  
     
     
         75 . The transceiver according to  claim 69  wherein the range of frequency of said current and voltage pulses is 5-50 kHz.  
     
     
         76 . The transceiver according to  claim 69  wherein the pre-determined DC potential of said power is substantially 24 volts.  
     
     
         77 . The transceiver according to  claim 69  wherein said transceiver further includes a sensor module.  
     
     
         78 . The transceiver according to  claim 69  wherein said transceiver further includes a control module.  
     
     
         79 . The transceiver according to  claim 69  wherein said transceiver further includes a priority setting module.  
     
     
         80 . The transceiver according to  claim 71  wherein said current coupling means comprises a constant current source connected in series with a zener diode.