Low voltage differential to single-ended converter

Abstract

Method and circuitry for converting a differential logic signal to a single-ended logic signal eliminate slower PMOS transistors and speed up the conversion process. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C3MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using a differential pair of NMOS transistors with resistors as load devices and an NMOS current source transistor that provides dynamically adjusted tail current.

What is claimed is:  
     
         1 . A circuit for converting a differential logic signal to a single-ended logic signal, comprising: 
 a first NMOS transistor having a gate terminal coupled to receive a first half of the differential logic signal, a source terminal and a drain terminal;    a second NMOS transistor having a gate terminal coupled to receive a second half of the differential logic signal, a source terminal coupled to the source terminal of the first NMOS transistor, and a drain terminal;    a first resistor coupled between the drain terminal of the first NMOS transistor and a logic high node;    a second resistor coupled between the drain terminal of the second NMOS transistor and the logic high node; and    a third NMOS transistor having a gate terminal coupled the drain terminal of the first NMOS transistor, a source terminal coupled to a logic low node, and a drain terminal coupled to the source terminals of the first and second NMOS transistors.    
     
     
         2 . The circuit of  claim 1  wherein the first, second and third NMOS transistors are of substantially the same size.  
     
     
         3 . The circuit of  claim 1  further comprising a fourth NMOS transistor having its drain and source terminals coupled between the source terminal of the third NMOS transistor and the logic low node, and a gate terminal coupled to an enable signal.  
     
     
         4 . The circuit of  claim 1  further comprising a PMOS transistor inserted between the logic high node and the first and second resistors with a gate terminal coupled to an enable signal.  
     
     
         5 . The circuit of  claim 2  wherein the first and second resistors are substantially made up of polysilicon material.  
     
     
         6 . The circuit of  claim 1  wherein the logic high node is a positive power supply node, and the logic low node is ground.  
     
     
         7 . The circuit of  claim 6  wherein the positive power supply node carries a voltage that is less than 1.5 volts.  
     
     
         8 . The circuit of  claim 1  further comprising a current source device coupled to the drain terminal of the first NMOS transistor.  
     
     
         9 . The circuit of  claim 8  wherein the current source device comprises a fourth NMOS transistor having a drain terminal coupled to the drain terminal of the first NMOS transistor, a source terminal coupled to the logic low node, and a gate terminal coupled to a bias voltage.  
     
     
         10 . A complementary metal-oxide-semiconductor (CMOS) circuit comprising: 
 a first circuit implemented in current-controlled CMOS (C 3 MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to a differential input signal;    a differential signal to single-ended signal converter coupled to the first circuit, the converter including a differential stage with resistive loads instead of PMOS transistors and a dynamically adjusted tail current and configured to convert the differential signal from the first circuit to a single-ended CMOS logic signal; and    a second circuit coupled to the converter to receive the single-ended CMOS logic signal and implemented in standard CMOS logic wherein substantially zero static current is dissipated.    
     
     
         11 . The CMOS circuit of  claim 10  wherein the differential signal to single-ended signal converter further comprises: 
 a differential pair of input NMOS transistors each coupled to a logic high node via a respective load resistor; and  
 a current source NMOS transistor coupled between the differential pair of input NMOS transistors and a logic low node, and having a gate coupled to a drain terminal of one of the differential pair of input NMOS transistors.  
 
     
     
         12 . A method of converting a differential logic signal to a single-ended logic signal comprising: 
 receiving the differential logic signal at inputs of a differential pair of NMOS transistors;    pulling up a signal at drain terminals of the pair of NMOS transistors using resistors instead of PMOS transistors; and    feeding back an output signal to dynamically adjust a current through the NMOS transistors.    
     
     
         13 . The method of  claim 12  further comprising disabling a current flow through the NMOS transistors when conversion is not required.