Pixel array for LC silicon light valve featuring pixels with overlapping edges

Abstract

The present invention provides a pixel array and a process flow for forming an array of pixel cells that features pixel electrodes having overlapping edges. This overlapping pixel configuration precludes absorption of light in inter-pixel regions that could give rise to the appearance of dark lines between bright reflective pixel electrodes. This pixel arrangement also prevents the disruption of charge stored in underlying capacitor structures due to the penetration of incident light through inter-pixel regions into the underlying substrate.

What is claimed is:  
     
         1 . A process for forming a pixel array comprising the steps of: 
 forming an intermetal dielectric layer over an interconnect metallization layer;    forming a first dielectric layer over the intermetal dielectric layer, the first dielectric layer different than the intermetal dielectric layer;    forming a second dielectric layer over the first dielectric layer, the second dielectric layer different than the first intermetal dielectric layer;    patterning a trench photoresist mask over the second dielectric layer, the trench photoresist mask masking pixel regions and exposing inter-pixel regions;    creating a trench by etching the second dielectric layer and the first dielectric layer in inter-pixel regions to stop on the intermetal dielectric layer;    removing the trench photoresist mask;    forming a reflective metal layer over the second dielectric layer and within the trench;    patterning a pixel photoresist mask over the reflective metal layer, the pixel photoresist mask masking first alternative pixel regions and exposing second alternative pixel regions;    etching the reflective metal layer and the second dielectric layer in second alternative pixel regions to stop on the first dielectric layer;    forming a third dielectric layer over the reflective metal layer in first alternative pixel regions and over the first dielectric layer in second alternative pixel regions;    forming a second reflective metal layer over the third dielectric layer, the second reflective metal layer having a raised portion in first alternative pixel regions and a lower portion in second alternative pixel regions;    forming a fourth dielectric layer over the second reflective metal layer; and    chemical mechanical polishing through the fourth dielectric layer, the raised portion of the second reflective metal layer, and the third dielectric layer to stop on the first reflective metal layer and the lower portion of the second reflective metal layer, such that first pixels are formed in first alternate pixel regions from the first reflective metal layer and second pixels are formed in the second alternate pixel regions from the lower portion of the second reflective metal layer, the first and second pixels separated and electrically isolated from one another by the third dielectric layer.    
     
     
         2 . The process according to  claim 1  wherein the step of forming the first dielectric layer comprises forming a layer of silicon nitride, and the step of forming the second dielectric layer comprises forming a layer of silicon oxide.  
     
     
         3 . A silicon light valve pixel array formed by the process of  claim 1 .  
     
     
         4 . A process for forming a pixel array comprising the steps of: 
 forming an intermetal dielectric layer on top of an interconnect metallization layer;    forming a plurality of electrically conducting vias extending through the intermetal dielectric layer to contact the interconnect metallization layer;    forming a first reflective metal layer over the vias and the intermetal dielectric;    forming a first pixel photoresist mask to cover first pixel regions and to exclude second pixel regions;    etching the first reflective metal layer in second pixel regions exposed by the first pixel photoresist mask;    removing the first pixel photoresist mask;    forming a first dielectric layer over the intermetal dielectric, the vias, and first reflective metal layer remaining in the first pixel regions;    forming a second reflective metal layer over the first dielectric layer;    forming a second pixel photoresist mask over the second reflective metal layer to cover the second pixel regions and to expose the first pixel regions;    etching the second reflective metal layer in exposed first pixel regions selective to the first dielectric layer; and    etching the first dielectric layer in exposed first pixel regions selective to the first reflective metal layer.    
     
     
         5 . A silicon light valve pixel array formed by the process of  claim 4 .  
     
     
         6 . A pixel array comprising: 
 a plurality of first reflective metal pixel electrodes; and    a plurality of second reflective metal pixel electrodes, the second electrodes having edges which project out of a plane of the first pixel electrodes, the edges of the second electrodes overlapping and separated from the first electrodes by a dielectric layer.    
     
     
         7 . The pixel array according to  claim 6  wherein the second pixel electrode edges underlie the first pixel electrode edges.  
     
     
         8 . The pixel array according to  claim 6  wherein the second pixel electrode edges overlie the first pixel electrode edges.  
     
     
         9 . A pixel array for a silicon light valve comprising: 
 a plurality of capacitor structures formed in a silicon substrate;    a plurality of first planar reflective metal pixel electrodes having edges;    a plurality of second reflective metal pixel electrodes separated from the first electrodes by inter-pixel regions, the second electrodes having edges overlapping the edges of the first pixel electrodes; and    a plurality of vias connecting the capacitor structures with the first and second metal electrodes.    
     
     
         10 . The pixel array according to  claim 9  wherein the edges of the second reflective metal pixel electrodes underlie the edges of the first reflective metal pixel electrodes.  
     
     
         11 . The pixel array according to  claim 9  wherein the edges of the second reflective metal pixel electrodes overlie the edges of the first reflective metal pixel electrodes.  
     
     
         12 . A method for preventing absorption of incident light in inter-pixel regions of a pixel array comprising the step of: 
 providing a plurality of reflective metal electrodes having overlapping edges.    
     
     
         13 . The method according to  claim 12  wherein the step of providing a plurality of reflective metal electrodes surface comprises forming planar first pixel electrodes having edges which underlie nonplanar edges of second pixel electrodes.  
     
     
         14 . The method according to  claim 12  wherein the step of providing a plurality of reflective metal electrodes surface comprises forming planar first pixel electrodes having edges which overlie nonplanar edges of second pixel electrodes.