Low voltage CMOS analog switch

Abstract

A low voltage analog switch having low leakage off-current and including a first transmission gate having a first N-channel transistor and a first P-channel transistor, each first and second transistor having respective drain and source terminals coupled together to form switch drain and source terminals, and a second transmission gate having a second N-channel transistor coupled in series to a second P-channel transistor coupled in series to a third N-channel transistor, the second transmission gate being coupled in parallel to the first transmission gate, the gates of the second and third N-channel transistors being coupled to the gate of the first N-channel transistor and a gate of the second P-channel transistor being coupled to the gate of the first P-channel transistor. In another embodiment, the second transmission gate includes a second P-channel transistor coupled in series to a second N-channel transistor coupled in series to a third P-channel transistor, the second transmission gate being coupled in parallel to the first transmission gate, the gates of the second and third P-channel transistors being coupled to the gate of the first P-channel transistor and a gate of the second N-channel transistor being coupled to the gate of the first N-channel transistor

I claim:  
     
         1 . A low voltage analog switch comprising: 
 a first transmission gate having a first N-channel transistor and a first P-channel transistor, each first and second transistor having respective drain and source terminals coupled together and forming switch drain and source terminals; and    a second transmission gate comprising a second N-channel transistor coupled in series to a second P-channel transistor coupled in series to a third N-channel transistor, the second transmission gate being coupled in parallel to the switch drain and source terminals, the gates of the second and third N-channel transistors being coupled to a gate of the first N-channel transistor and a gate of the second P-channel transistor being coupled to a gate of the first P-channel transistor.    
     
     
         2 . A low voltage analog switch as recited in  claim 1  wherein the second transmission gate is operable to reduce a minimum supply voltage of the switch.  
     
     
         3 . A low voltage analog switch as recited in  claim 1  wherein the second transmission gate is operable to maintain a leakage off-current of the switch.  
     
     
         4 . A low voltage analog switch as recited in  claim 2  wherein the first N-channel transistor and the first P-channel transistor are high threshold voltage transistors and wherein the second and third N-channel transistors and the second P-channel transistor are low threshold voltage transistors.  
     
     
         5 . A low voltage analog switch as recited in  claim 4  wherein the threshold voltage of the second and third N-channel transistors is ΔV TN  less than the threshold voltage of the first N-channel transistor, the threshold voltage of the second P-channel transistor is ΔV TP  less than the threshold of the first P-channel transistor and the minimum supply voltage is greater than ΔV TN +ΔV TP .  
     
     
         6 . A low voltage analog switch as recited in  claim 4  wherein the threshold voltage of the second and third N-channel transistors is ΔV TN  less than the threshold voltage of the first N-channel transistor, the threshold voltage of the second P-channel transistor is ΔV TP  less than the threshold of the first P-channel transistor and the reduction in the minimum supply voltage is the lesser of ΔV TN  and ΔV TP .  
     
     
         7 . A low voltage analog switch as recited in  claim 4  wherein the threshold voltage of the second and third N-channel transistors is ΔV TN  less than the threshold voltage of the first N-channel transistor, the threshold voltage of the second P-channel transistor is ΔV TP  less than the threshold of the first P-channel transistor and the reduction in the minimum supply voltage is the lesser of ΔV TN  and ΔV TP  and wherein the minimum supply voltage is greater than ΔV TN +ΔV TP .  
     
     
         8 . A low voltage analog switch as recited in  claim 2  wherein a positive rail of the supply voltage is coupled to the gate of the first N-channel transistor and a negative rail of the supply voltage is coupled to the gate of the second P-channel transistor.  
     
     
         9 . A low voltage analog switch as recited in  claim 3  wherein the first N-channel transistor and the first P-channel transistor are high threshold voltage transistors and wherein the second and third N-channel transistors and the second P-channel transistor are low threshold voltage transistors.  
     
     
         10 . A low voltage analog switch as recited in  claim 1  further comprising a plurality of passive device in series with the first, second and third N-channel transistors and first and second P-channel transistors.  
     
     
         11 . A low voltage analog switch as recited in  claim 1  wherein the N-channel transistors are N-channel MOSFETs and the P-channel transistors are P-channel MOSFETs.  
     
     
         12 . A low voltage analog switch as recited in  claim 1  wherein the second transmission gate is operable to reduce a minimum supply voltage of the switch while maintaining a leakage off-current of the switch.  
     
     
         13 . A low voltage analog switch as recited in  claim 12  wherein the leakage off-current of the switch is maintained over a rail-to-rail range of a switched signal.  
     
     
         14 . A low voltage analog switch comprising: 
 a first transmission gate having a first N-channel transistor and a first P-channel transistor, each first and second transistor having respective drain and source terminals coupled together and forming switch drain and source terminals; and    a second transmission gate comprising a second P-channel transistor coupled in series to a second N-channel transistor coupled in series to a third P-channel transistor, the second transmission gate being coupled in parallel to the first transmission gate drain and source terminals, the gates of the second and third N-channel transistors being coupled to a gate of the first N-channel transistor and a gate of the second P-channel transistor being coupled to a gate of the first P-channel transistor.    
     
     
         15 . A low voltage analog switch as recited in  claim 14  wherein the second transmission gate is operable to reduce a minimum supply voltage of the switch.  
     
     
         16 . A low voltage analog switch as recited in  claim 14  wherein the second transmission gate is operable to maintain a leakage off-current of the switch.  
     
     
         17 . A low voltage analog switch as recited in  claim 15  wherein the first N-channel transistor and the first P-channel transistor are high threshold voltage transistors and wherein the second and third P-channel transistors and the second N-channel transistor are low threshold voltage transistors.  
     
     
         18 . A low voltage analog switch as recited in  claim 17  wherein the threshold voltage of the second and third P-channel transistors is ΔV TP  less than the threshold voltage of the first P-channel transistor, the threshold voltage of the second N-channel transistor is ΔV TN  less than the threshold of the first N-channel transistor and the minimum supply voltage is greater than ΔV TN +ΔV TP .  
     
     
         19 . A low voltage analog switch as recited in  claim 17  wherein the threshold voltage of the second and third P-channel transistors is ΔV TP  less than the threshold voltage of the first P-channel transistor, the threshold voltage of the second N-channel transistor is ΔV TN  less than the threshold of the first N-channel transistor and the reduction in the minimum supply voltage is the lesser of ΔV TN  and ΔV TP .  
     
     
         20 . A low voltage analog switch as recited in  claim 17  wherein the threshold voltage of the second and third P-channel transistors is ΔV TP  less than the threshold voltage of the first P-channel transistor, the threshold voltage of the second N-channel transistor is ΔV TN  less than the threshold of the first N-channel transistor and the reduction in the minimum supply voltage is the lesser of ΔV TN  and ΔV TP  and wherein the minimum supply voltage is greater than ΔV TN +ΔV TP .  
     
     
         21 . A low voltage analog switch as recited in  claim 15  wherein a positive rail of the supply voltage is coupled to the gate of the first N-channel transistor and a negative rail of the supply voltage is coupled to the gate of the second P-channel transistor.  
     
     
         22 . A low voltage analog switch as recited in  claim 16  wherein the first N-channel transistor and the first P-channel transistor are high threshold voltage transistors and wherein the second and third P-channel transistors and the second N-channel transistor are low threshold voltage transistors.  
     
     
         23 . A low voltage analog switch as recited in  claim 14  further comprising a plurality of passive device in series with the first, second and third P-channel transistors and first and second N-channel transistors.  
     
     
         24 . A low voltage analog switch as recited in  claim 14  wherein the N-channel transistors are N-channel MOSFETs and the P-channel transistors are P-channel MOSFETs.  
     
     
         25 . A low voltage analog switch as recited in  claim 14  wherein the second transmission gate is operable to reduce a minimum supply voltage of the switch while maintaining a leakage off-current of the switch.  
     
     
         26 . A low voltage analog switch as recited in  claim 25  wherein the leakage off-current of the switch is maintained over a rail-to-rail range of a switched signal.  
     
     
         27 . A method for reducing the supply voltage of an analog switch while maintaining the leakage off-current comprising the acts of: 
 providing a first transmission gate having a first N-channel transistor and a first P-channel transistor, each first and second transistor having respective drain and source terminals coupled together and forming switch drain and source terminals;    providing a second transmission gate comprising a second N-channel transistor coupled in series to a second P-channel transistor coupled in series to a third N-channel transistor;    coupling the second transmission gate in parallel to the switch drain and source terminals, the gates of the second and third N-channel transistors being coupled to a gate of the first N-channel transistor and a gate of the second P-channel transistor being coupled to a gate of the first P-channel transistor.    
     
     
         28 . A method as recited in  claim 27  wherein the first N-channel transistor and the first P-channel transistor are high threshold voltage transistors and wherein the second and third N-channel transistors and the second P-channel transistor are low threshold voltage transistors.  
     
     
         29 . A method for reducing the supply voltage of an analog switch while maintaining the leakage off-current comprising the acts of: 
 providing a first transmission gate having a first N-channel transistor and a first P-channel transistor, each first and second transistor having respective drain and source terminals coupled together and forming switch drain and source terminals;    providing a second transmission gate comprising a second P-channel transistor coupled in series to a second N-channel transistor coupled in series to a third P-channel transistor;    coupling the second transmission gate in parallel to the switch drain and source terminals, the gates of the second and third P-channel transistors being coupled to a gate of the first P-channel transistor and a gate of the second N-channel transistor being coupled to a gate of the first N-channel transistor.    
     
     
         30 . A method as recited in  claim 29  wherein the first N-channel transistor and the first P-channel transistor are high threshold voltage transistors and wherein the second and third P-channel transistors and the second N-channel transistor are low threshold voltage transistors.