IC wafer cushioned separators

Abstract

An IC wafer shipping container has therein a stack of IC wafers. At least one side of each wafer has raised, conductive bump pads. A separator is located between two wafers. The film separators each have a dissipative layer and an insulating layer. The separators are cushioned to protect the wafers from mechanical shock and electrical shock. The separators are cushioned by embossing.

1 . A packaging configuration for integrated circuit wafers, comprising: 
 a) at least two integrated circuit wafers;    b) a film having a pattern of projections extending from the film, the projections being independent from one another, the film being interposed between the two wafers which are stacked, the projections absorbing mechanical shock applied to wafers.    
     
     
         2 . The packaging configuration of  claim 1  wherein the film has a dissipative layer and an insulating layer, the dissipative layer of the film has a surface resistance of between 1×10 4 -1×10 11  ohms.  
     
     
         3 . The packaging configuration of  claim 2  wherein the insulating layer of the film is in contact with a circuit side of one of the adjacent wafers.  
     
     
         4 . The packaging configuration of  claim 1  wherein the wafers comprise bump pads, with the film contacting the bump pads of at least one of the wafers.  
     
     
         5 . The packaging system of  claim 1  wherein the film projections comprise bosses.  
     
     
         6 . A system for providing protection to integrated circuit wafers, comprising: 
 a) a container having an interior space for receiving the wafers;    b) at least two of the wafers stacked inside the interior space;    c) a film having a pattern of projections extending from the film, the projections being independent from one another, the film being interposed between the two wafers, the projections absorbing mechanical shock applied to wafers.    
     
     
         7 . The system of  claim 6  wherein the film has a dissipative layer and an insulating layer, the dissipative layer of the film has a surface resistance of between 1×10 4 -1×10 11  ohms.  
     
     
         8 . The system of  claim 7  wherein the insulating layer of the film is in contact with a circuit side of one of the adjacent wafers.  
     
     
         9 . The system of  claim 6  wherein the wafers comprise bump pads, with the film contacting the bump pads of at least one of the wafers.  
     
     
         10 . The system of  claim 6  wherein the film projections comprise bosses.