Method of fabricating gate

Abstract

A method of fabricating a gate. A gate dielectric layer is formed, and a lower portion of a floating gate is formed encompassed by a first dielectric layer. Second dielectric layers with different etching rates are formed to cover the upper portion of the floating gate and the first dielectric layer. Using an etching mask, an opening is formed within the second dielectric layer to expose the floating gate and a portion of the second dielectric layers by performing an anisotropic etching process. Using the same etching mask, the second dielectric layers exposed within the opening is further etched by performing an isotropic etching process. Due to the different etching rates, a dielectric layer with an uneven and enlarged surface is formed. A conformal conductive layer is formed on the exposed lower portion of the floating gate and the exposed second dielectric layers as an upper portion of the floating gate. A conformal third dielectric layer is formed on the conformal conductive layer, followed by forming a control gate on the third dielectric layer.

What is claimed is:  
     
         1 . A method of fabricating a gate over a substrate which comprising a device structure, the device structure including a source/drain region, a gate dielectric layer, a first gate conductive layer, and a first dielectric layer encompassing the first gate conductive layer, the method comprising: 
 forming a plurality of second dielectric layers on the first dielectric layer and the first gate conductive layer;    forming a first etching mask on a topmost second dielectric layer, the etching mask comprising a first opening expose a portion of the topmost second dielectric layer;    performing an anisotropic etching step to form a second opening that exposes the first gate conductive layer    performing an isotropic etching step on the second dielectric layers exposed within the second opening with the etching mask remaining on the topmost second dielectric layer, so that a third opening having an uneven surface since the second dielectric layers have different etching rates from each other is formed;    removing the first etching mask.    
     
     
         2 . The method according to  claim 1 , wherein the step of performing the isotropic etching step comprising forming the third opening with a stair-like profile.  
     
     
         3 . The method according to  claim 1 , wherein the step of forming the second dielectric layers comprises forming the second dielectric layers with materials including at least one of the oxide, silicon nitride, doped oxide, doped silicon nitride, borosilicate glass (BSG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), boro-oxide, phospho-oxide, borophospho-oxide, spin-on-glass or organic silicide containing silicon and oxide.  
     
     
         4 . The method according to  claim 1 , wherein the step of forming the second dielectric layers includes a forming each of the second dielectric layers with a certain density to result in different isotropic etching rates from each other.  
     
     
         5 . The method according to  claim 1 , wherein the step of performing the isotropic etching includes a step of controlling the dopant concentration of the second dielectric layers to result in different etching rates.  
     
     
         6 . The method according to  claim 1 , wherein the step of performing the isotropic etching includes a chemical dry etching process, a chemical wet etching process, or a chemical vapor etching process.  
     
     
         7 . The method according to  claim 6 , wherein the step of chemical wet etching process comprises a step of using one of a mixture of hydrogen fluoride and ammonium fluoride, nitric acid or phosphoric acid as an etchant.  
     
     
         8 . The method according to  claim 1 , further comprising the following steps: 
 forming a conformal conductive layer covering a bottom surface and a sidewall of the third opening, including the second dielectric layers and the first gate conductor layer exposed by the third opening;    patterning the first conductive layer to expose the second dielectric layers out of the third opening;    forming a conformal third dielectric layer on the first conductive layer as a gate dielectric layer; and    forming a second conductive layer on the third dielectric layer.    
     
     
         9 . The method according to  claim 1 , wherein the step of forming the third dielectric layer comprises forming a silicon nitride layer, a silicon oxide layer, a composite layer of oxide/nitride/oxide, a lead zirconium titanate layer or a tantalum oxide layer.  
     
     
         10 . The method according to  claim 1 , wherein the step of forming the second conductive layer comprises a step of forming one of a polysilicon layer and a tungsten layer.  
     
     
         11 . A method of forming a dielectric layer, the method comprising: 
 providing a substrate, the substrate comprising a device structure;    forming a plurality of dielectric layers on the substrate;    forming an etching mask on a topmost layer among the dielectric layers;    performing an anisotropic etching step on the dielectric layers until the device structure is exposed;    performing an isotropic etching step on the dielectric layers, wherein the dielectric layers have different isotropic etching rates; and    removing the etching mask layer.    
     
     
         12 . The method according to  claim 11 , wherein the step of performing the isotropic etching step includes a step of forming an opening with a stair-like profile within the dielectric layers.  
     
     
         13 . The method according to  claim 11 , wherein the step of forming the dielectric layers with materials including at least one of the oxide, silicon nitride, doped oxide, doped silicon nitride, borosilicate glass (BSG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), boro-oxide, phospho-oxide, borophospho-oxide, spin-on-glass or organic silicide containing silicon and oxide.  
     
     
         14 . The method according to  claim 11 , wherein the step of forming the dielectric layers comprises a step of forming the dielectric layers with different densities to result in the different isotropic etching rates.  
     
     
         15 . The method according to  claim 11 , wherein the step of forming the dielectric layer includes a step of forming the dielectric layers with different dopant concentrations to result in the different isotropic etching rates.  
     
     
         16 . The method according to  claim 11 , wherein the step of performing the isotropic etching includes a chemical dry etching process, a chemical wet etching process, or a chemical vapor etching process.  
     
     
         17 . The method according to  claim 16 , wherein the step of chemical wet etching process comprises a step of using one of a mixture of hydrogen fluoride and ammonium fluoride, nitric acid or phosphoric acid as an etchant.  
     
     
         18 . A method for fabricating a capacitor, comprising: 
 providing a substrate comprising a device region thereon;    forming a plurality of dielectric layers with different etching rates on the substrate;    performing an ansotropic etching process on the dielectric layers using an etching mask formed on the dielectric layers until sidewalls of the dielectric layers and the device region is exposed;    performing an isotropic etching process on the exposed sidewalls of the dielectric layer using the same etching mask used for the anisotropic etching process;    forming a first conductive layer on the sidewalls of the dielectric layers, the first conductive layer being conformal to the surface profile of the sidewalls;    forming a capacitor dielectric layer on the first conductive layer, the capacitor dielectric layer being conformal to the first conductive layer; and    forming a second conductive layer on the capacitor dielectric layer.    
     
     
         19 . The method according to  claim 18 , wherein the step of performing the isotropic etching process includes a step of etching the exposed sidewalls of the dielectric layers to have a stair-like profile.  
     
     
         20 . The method according to  claim 18 , wherein the step of forming the dielectric layers with materials including at least one of the oxide, silicon nitride, doped oxide, doped silicon nitride, borosilicate glass (BSG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), boro-oxide, phospho-oxide, borophospho-oxide, spin-on-glass or organic silicide containing silicon and oxide.  
     
     
         21 . The method according to  claim 18 , wherein the step of forming the dielectric layers comprises a step of forming the dielectric layers with different densities to result in the different isotropic etching rates.  
     
     
         22 . The method according to  claim 18 , wherein the step of forming the dielectric layer includes a step of forming the dielectric layers with different dopant concentrations to result in the different isotropic etching rates.  
     
     
         23 . The method according to  claim 18 , wherein the step of performing the isotropic etching includes a chemical dry etching process, a chemical wet etching process, or a chemical vapor etching process.  
     
     
         24 . The method according to  claim 23 , wherein the step of chemical wet etching process comprises a step of using one of a mixture of hydrogen fluoride and ammonium fluoride, nitric acid or phosphoric acid as an etchant.  
     
     
         25 . A gate structure, formed over a substrate comprising a source/drain region, the gate structure comprises: 
 a gate dielectric layer, on the substrate;    a first gate conductive layer, on the gate dielectric layer;    a first dielectric layer, encompassing the first gate conductive layer;    a plurality of second dielectric layers, with an opening exposing a portion of the first dielectric layer and the first gate conductive layer, the opening having a sidewall with a stair-like profile;    a second gate conductive layer, on a surface of the opening and conformal to the stair-like profile; and    a third dielectric layer, on and conformal to the second gate conductive layer.    
     
     
         26 . The gate structure according to  claim 25 , comprising further a third gate conductive layer on the third dielectric layer.  
     
     
         27 . The gate structure according to  claim 25 , wherein the second dielectric layer comprises one of the oxide, silicon nitride, doped oxide, doped silicon nitride, borosilicate glass (BSG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), boro-oxide, phospho-oxide, borophospho-oxide, spin-on-glass or organic silicide containing silicon and oxide.  
     
     
         28 . The gate structure according to  claim 25 , wherein the second dielectric layers have different densities from each other.  
     
     
         29 . The gate structure according to  claim 25 , wherein the second dielectric layers have different dopant concentration from each other.  
     
     
         30 . The gate structure according to  claim 25 , wherein the second dielectric layer comprises one of silicon nitride layer, silicon oxide layer, an oxide/nitride/oxide layer, a lead zirconium titanate layer, a bismuth strontium titanate layer and a tantalum oxide layer.  
     
     
         31 . The gate structure according to  claim 25 , wherein the second gate conductive layer and the third gate conductive layer comprise one of a polysilicon layer and a tungsten silicide layer.  
     
     
         32 . A dielectric structure, formed over a substrate comprising a device region, the dielectric structure comprises: 
 a plurality of dielectric layers, with an opening exposing the device region, wherein the opening has a slanting sidewall with a stair-like profile.    
     
     
         33 . The dielectric structure according to  claim 32 , wherein the dielectric layers comprises one of the oxide, silicon nitride, doped oxide, doped silicon nitride, borosilicate glass (BSG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), boro-oxide, phospho-oxide, borophospho-oxide, spin-on-glass or organic silicide containing silicon and oxide.  
     
     
         34 . The dielectric structure according to  claim 32 , wherein the dielectric layers have different densities from each other.  
     
     
         35 . The dielectric structure according to  claim 32 , wherein the dielectric layers have different dopant concentrations from each other.  
     
     
         36 . A bottom electrode over a substrate, the substrate having a device region thereon, the bottom electrode comprising: 
 a plurality of dielectric layers, on the substrate and having an opening with a slanting stair-like sidewall, wherein the device region of the substrate is exposed; and    a bottom electrode, formed along a surface profile of the opening.    
     
     
         37 . The bottom electrode according to  claim 36 , wherein the dielectric layer comprises one of oxide, silicon nitride, doped oxide, doped silicon nitride, borosilicate glass (BSG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), boro-oxide, phospho-oxide, borophospho-oxide, spin-on-glass or organic silicide containing silicon and oxide.  
     
     
         38 . The bottom electrode according to  claim 36 , wherein the dielectric layers have different densities from each other.  
     
     
         39 . The bottom electrode according to  claim 36 , wherein the dielectric layers have different dopant concentrations from each other.