Process for fabricating copper interconnect for ULSI integrated circuits

Abstract

A method for manufacturing integrated circuits; particularly, a method for fabricating a copper interconnect system and a copper interconnect system, having a layer of CrO, fabricated by the method.

What is claimed is:  
     
         1 . A method of manufacturing an integrated circuit comprising: 
 a. providing a wafer having an inter-level dielectric film and a barrier layer;    b. depositing a seed layer of copper on said barrier layer;    c. electroplating copper to a thickness sufficient to fill any valleys in said inter-level dielectric film and cover an entire top surface of said wafer;    d. chemical mechanical polishing said top surface to remove i) any excess portions of copper caused by said electroplating and ii) selected portions of said inter-level dielectric film;    e. depositing a layer of CrO on said polished top surface to cover remaining portions of said copper;    f. depositing a passivation layer on said layer of CrO and portions of said inter-level dielectric film; and    g. etching said passivation layer to form a via that exposes a selected portion of said layer of CrO.    
     
     
         2 . The method of  claim 1  wherein said inter-level dielectric film comprises at least one layer of an inorganic compound selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and mixtures thereof.  
     
     
         3 . The method of  claim 1  wherein said inter-level dielectric film is SiO 2 .  
     
     
         4 . The method of  claim 1  wherein said inter-level dielectric film comprises at least one layer of an organic compound.  
     
     
         5 . The method of  claim 1  wherein said barrier layer comprises a material selected from the group consisting of Ta, TaN, TiN, Ti, W, WN, TiSiN, TaSiN, or mixtures thereof.  
     
     
         6 . The method of  claim 1  wherein said layer of CrO has a thickness of about 150-600Å.  
     
     
         7 . The method of  claim 1  wherein said layer of CrO has a thickness of about 300Å.  
     
     
         8 . The method of  claim 1  wherein said layer of CrO is formed by sputtering Cr in the presence of O 2  and said layer of CrO is patterned using lithography after said layer of CrO is deposited.  
     
     
         9 . The method of  claim 1  wherein said layer of CrO is formed by evaporating Cr in the presence of O 2  and said layer of CrO is patterned using lithography after said layer of CrO is deposited.  
     
     
         10 . The method of  claim 1  wherein said layer of CrO is formed by autocatalytic plating Cr in the presence of O 2 .  
     
     
         11 . The method of  claim 1  wherein said barrier layer is backsputtered before said seed layer is formed to improve adhesion.  
     
     
         12 . The method of  claim 1  wherein said seed layer is formed by sputtering.  
     
     
         13 . The method of  claim 1  wherein said seed layer is formed by chemical vapor deposition.  
     
     
         14 . The method of  claim 1  wherein said passivation layer is comprised of a compound selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, doped silicon dioxide, doped silicon nitride, doped silicon oxynitride, and mixtures thereof.  
     
     
         15 . The method of  claim 1  wherein said passivation layer is formed by a process selected from the group consisting of chemical vapor deposition, spin-on dielectric glass, spinon dielectric polymer, and combinations thereof.  
     
     
         16 . An integrated circuit made by the method of  claim 1 .  
     
     
         17 . An integrated circuit comprising: 
 a wafer having a surface;    a copper layer and an inter-level dielectric film formed on selected portions of said surface;    a seed layer and a barrier layer formed between said copper layer and said inter-level dielectric film;    a layer of CrO deposited substantially uniformly on top of said copper layer;    a passivation layer covering any exposed portions of said copper layer and said inter-level dielectric film; and    a via formed in said passivation layer, exposing a portion of said layer of CrO.    
     
     
         18 . A method of manufacturing an integrated circuit comprising: 
 a. providing a wafer having bond pads comprised of a barrier layer, a seed layer formed thereon, and copper formed on said seed layer;    b. forming a layer of CrO on said copper;    c. forming a passivation layer on said layer of CrO; and    d. etching said passivation layer to form a via that exposes a selected portion of said layer of CrO.    
     
     
         19 . The method of  claim 18  wherein said barrier layer comprises a material selected from the group consisting of Ta, TaN, TiN, Ti, W, WN, TiSiN, TaSiN, and mixtures thereof.  
     
     
         20 . The method of  claim 18  wherein said layer of CrO has a thickness of about 150-600Å.  
     
     
         21 . The method of  claim 18  wherein said layer of CrO has a thickness of about 300Å.  
     
     
         22 . The method of  claim 18  wherein said layer of CrO is formed by sputtering Cr in the presence of O 2  and said layer of CrO is patterned using lithography after said layer of CrO is deposited.  
     
     
         23 . The method of  claim 18  wherein said layer of CrO is formed by evaporating Cr in the presence of O 2  and said layer of CrO is patterned using lithography after said layer of CrO is formed.  
     
     
         24 . The method of  claim 18  wherein said layer of CrO is formed by autocatalytic plating Cr in the presence of O 2 .  
     
     
         25 . The method of  claim 18  wherein said passivation layer is comprised of a compound selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, doped silicon dioxide, doped silicon nitride, doped silicon oxynitride, and mixtures thereof.  
     
     
         26 . The method of  claim 18  wherein said passivation layer is formed by a process selected from the group consisting of chemical vapor deposition, spin-on dielectric glass, spin-on dielectric polymer, and combinations thereof.  
     
     
         27 . The method of  claim 18  further comprising: 
 c. depositing multiple metal interconnect layers on said passivation layer and layer of CrO.  
 
     
     
         28 . An integrated circuit made by the method of  claim 18 .  
     
     
         29 . An integrated circuit comprising: 
 a bond pad, having a barrier layer, a seed layer formed on said barrier layer,    a copper layer formed on said seed layer, and a layer of CrO covering said copper layer, formed in an inter-level dielectric film; and    a passivation layer formed on any exposed portions of said copper layer, said inter-level dielectric fil, and a portion of said layer of CrO.