Method for forming contact having low resistivity using porous plug and method for forming semiconductor devices using the same

Abstract

A method for forming a contact of a semiconductor device is disclosed. A first interlevel dielectric (ILD) layer is formed on a conductive region, e.g., an active region. The first ILD layer is etched to form a first contact hole therein to expose the conductive region. The first contact hole is filled with a porous layer having a high etch selectivity with respect to the first ILD layer to form a porous plug therein. Next, a second ILD layer is formed overlying the porous plug. The second ILD layer is etched to form a second contact hole therein to expose the porous plug. The porous plug in the first contact hole is removed. The first and second contact holes are filled with a conductive material to form a contact plug. During this contact formation process, the active region or the conductive region of the semiconductor substrate can be protected with the porous plug. Thus, the electrical characteristics degradation caused by dopant diffusion resulting from a thermal process during contact formation can be avoided.

What is claimed is:  
     
         1 . A method for forming a contact for a semiconductor device, comprising: 
 forming a first interlevel dielectric (ILD) layer on a semiconductor substrate having an active region;    etching the first ILD layer to form a first contact hole therein to expose the active region;    filling the first contact hole with a porous layer having a high etch selectivity with respect to the first ILD layer to form a porous plug therein;    forming a second ILD layer overlying the porous plug;    etching the second ILD layer to form a second contact hole therein to expose the porous plug;    removing the porous plug formed in the first contact hole; and    filling the first and second contact holes with a conductive material to form a contact plug therein.    
     
     
         2 . The method of  claim 1 , wherein the porous plug is formed of oxide.  
     
     
         3 . The method of  claim 1 , wherein filling the first contact hole with the porous layer further comprises: 
 forming a porous layer having a high etch selectivity with respect to the first ILD layer within the first contact hole and on the first ILD layer; and    planarizing the porous layer to form the porous plug in the first contact hole.    
     
     
         4 . The method of  claim 3 , wherein the porous layer is formed of oxide.  
     
     
         5 . The method of  claim 4 , wherein the porous oxide layer is formed by a chemical vapor deposition (CVD) method.  
     
     
         6 . The method of  claim 5 , wherein tetramethyl silane (TMS), tetrafluoro silane, trimethylfluoro silane, or dimethyldifluoro silane is used as a source gas, and oxygen (O 2 ) and hydrogen (H 2 ) are used as a reactive gas, in the CVD method.  
     
     
         7 . The method of  claim 5 , wherein the CVD method is performed under a pressure of 0.1-10 Torr, at a temperature of 50-600° C., and at a radio frequency (RF) power of 50-700 W.  
     
     
         8 . The method of  claim 5 , wherein the porous oxide layer is formed of a material selected from the group consisting of SiO 2 , SiOF, SiOC, and SiOCH.  
     
     
         9 . The method of  claim 5 , wherein the porous oxide layer is formed of xerogel, or aerogel.  
     
     
         10 . The method of  claim 1 , wherein the porous layer is a glass oxide layer formed by a spin on glass (SOG) method.  
     
     
         11 . The method of  claim 10 , wherein the porous layer is thermally treated at a temperature of 200-1000° C.  
     
     
         12 . The method of  claim 10 , wherein the porous layer is formed of a material selected from the group consisting of SiO 2 , SiOC, and SiOCH.  
     
     
         13 . The method of  claim 10 , wherein the porous layer is formed of xerogel, or aerogel.  
     
     
         14 . The method of  claim 1 , wherein removing the porous layer comprises wet etching.  
     
     
         15 . The method of  claim 14 , wherein a wet etchant used in the wet etching is a LAL solution or a hydrofluoric acid (HF) solution.  
     
     
         16 . The method of  claim 1 , wherein the conductive material for forming the contact plug is a metal.  
     
     
         17 . The method of  claim 16 , wherein the metal is aluminum (Al), tungsten (W), titanium nitride (TiN), or tungsten silicon (WSi).  
     
     
         18 . The method of  claim 16 , before forming the contact plug, further comprising forming an ohmic layer/diffusion barrier layer in the first contact hole and the second contact hole.  
     
     
         19 . The method of  claim 18 , wherein the ohmic layer is formed of a metal selected from the group consisting of consisting of titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), or tungsten (W), and the diffusion barrier layer is formed of a nitride of the selected metal.  
     
     
         20 . The method of  claim 1 , wherein the etch selectivity of the porous layer with respect to the first and second ILD layers is greater than 5.  
     
     
         21 . The method of  claim 1 , wherein the first and second ILD layers are high-density plasma (HDP) layers, plasma enhanced-tetraethylorthosilicate (PE-TEOS) layers, or undoped silicate glass (USG) layers.  
     
     
         22 . A method for forming a semiconductor device, comprising: 
 forming an isolation layer that defines active regions on a semiconductor substrate having a cell region and a peripheral circuit region,    forming a transistor on the active regions of the cell region and the peripheral circuit region;    forming a first interlevel dielectric (ILD) layer overlying the transistor;    forming a bit line and a bit line contact connected to a source or drain region of the transistor formed on the cell region through the first ILD layer;    forming a second ILD layer overlying the bit line;    forming a contact for a capacitor electrode connected to the source or drain region of the transistor formed on the cell region through the first and second ILD layers;    forming a first contact hole to expose the active region of the peripheral circuit region or a gate electrode of the transistor through the first and second ILD layers; and    filling the first contact hole with a porous layer having a high etch selectivity with respect to the first and second ILD layers.    
     
     
         23 . The method of  claim 22 , further comprising: 
 forming a capacitor connected to the contact for a capacitor electrode on the second ILD layer of the cell region;    forming a third ILD layer overlying the capacitor;    forming a second contact hole overlying the first contact hole of the peripheral circuit region through the third ILD layer of the peripheral circuit region;    removing the porous layer in the first contact hole; and    filling the exposed first and second contact holes with a conductive material to form a contact on the peripheral circuit region.    
     
     
         24 . The method of  claim 23 , wherein the porous layer is formed of oxide.  
     
     
         25 . The method of  claim 24 , wherein the porous oxide layer is formed by a chemical vapor deposition (CVD) method.  
     
     
         26 . The method of  claim 24 , wherein the porous oxide layer is a glass oxide layer formed by a spin on glass (SOG) method.  
     
     
         27 . The method of  claim 24 , wherein the porous oxide layer is removed by wet etching during removing the porous oxide layer.  
     
     
         28 . The method of  claim 24 , before forming the contact plug, further comprising forming an ohmic layer/diffusion barrier layer in the first contact hole and the second contact hole.  
     
     
         29 . The method of  claim 23 , after forming the second ILD layer, further comprising forming an etch stopper on the second ILD layer.  
     
     
         30 . The method of  claim 23 , wherein the etch selectivity of the porous oxide layer with respect to the first, second, and third ILD layers is greater than 5.  
     
     
         31 . The method of  claim 23 , wherein the first, second, and third ILD layers are high-density plasma (HDP) layers, plasma enhanced tetraethylorthosilicate (PE-TEOS) layers, or undoped silicate glass (USG) layers.  
     
     
         32 . A method for forming a semiconductor device, comprising: 
 forming a transistor on active regions of a cell region and a peripheral circuit region of a semiconductor substrate;    forming a first interlevel dielectric (ILD) layer overlying the transistor;    forming a bit line contact connected to a source or drain region of the transistor formed on the cell region through the first ILD layer;    forming a first contact hole to expose the active region of the peripheral circuit region or a gate electrode of the transistor through the first ILD layer; and    filling the first contact hole with a porous layer having a high etch selectivity with respect to the first ILD layer.    
     
     
         32 . The method of  claim 32 , further comprising: 
 forming a bit line connected to the bit line contact on the cell region;    forming a second ILD layer overlying the bit line;    forming a contact for a capacitor connected to the source or drain region of the cell region through the first and second ILD layers;    forming a capacitor connected to the contact for forming a capacitor on the cell region;    forming a third ILD layer overlying the capacitor;    forming a second contact hole overlying the first contact hole on the peripheral circuit region through the second and third ILD layers of the peripheral circuit region;    removing the porous layer in the first contact hole; and    filling the first and second contact holes with a conductive material to form a contact on the peripheral circuit region.    
     
     
         33 . The method of  claim 32 , wherein the porous layer is formed of oxide.  
     
     
         34 . The method of  claim 33 , wherein the porous oxide layer is formed by a chemical vapor deposition (CVD) method.  
     
     
         35 . The method of  claim 34 , wherein tetramethyl silane (TMS), tetrafluoro silane, trimethylfluoro silane, or dimethyldifluoro silane is used as a source gas, and oxygen (O2) and hydrogen (H2) are used as a reactive gas, in the CVD method.  
     
     
         36 . The method of  claim 34 , wherein the CVD method is performed at a pressure of 0.1-10 Torr, a temperature of 50-600° C., and a radio frequency (RF) power of 50-700 W.  
     
     
         37 . The method of  claim 34 , wherein the porous oxide layer is formed of a material selected from the group consisting of SiO 2 , SiOF, SiOC, and SiOCH.  
     
     
         38 . The method of  claim 34 , wherein the porous oxide layer is formed of xerogel, or aerogel.  
     
     
         39 . The method of  claim 33 , wherein the porous oxide layer is a glass oxide layer formed by a spin on glass (SOG) method.  
     
     
         40 . The method of  claim 39 , wherein the porous oxide layer is thermally treated at a temperature of 200-1000° C.  
     
     
         41 . The method of  claim 39 , wherein the porous oxide layer is formed of a material selected from the group consisting of SiO 2 , SiOC, and SiOCH.  
     
     
         42 . The method of  claim 39 , wherein the porous oxide layer is formed of xerogel, or aerogel.  
     
     
         43 . The method of  claim 32 , wherein removing the porous layer comprises wet etching.  
     
     
         44 . The method of  claim 43 , wherein a wet etchant used in the wet etching is a LAL solution or a hydrofluoric acid (HF) solution.  
     
     
         45 . The method of  claim 32 , before forming the contact plug, further comprising forming an ohmic layer/diffusion barrier layer in the first contact hole and the second contact hole.  
     
     
         46 . The method of  claim 45 , wherein the ohmic layer/diffusion barrier layer is formed of a metal selected from the group consisting of titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), or tungsten (W), and nitride of the metal, respectively.  
     
     
         47 . The method of  claim 32 , after forming the second ILD layer, further comprising forming an etch stopper on the second ILD layer.  
     
     
         48 . The method of  claim 47 , wherein the etch stopper is a silicon nitride (SiN) layer.  
     
     
         49 . The method of  claim 32 , wherein the etch selectivity of the porous layer with respect to the first, second, and third ILD layers is greater than 5.  
     
     
         50 . The method of  claim 32 , wherein the first, second, and third ILD layers are high-density plasma (HDP) layers, plasma enhanced tetraethylorthosilicate (PE-TEOS) layers, or undoped silicate glass (USG) layers.  
     
     
         51 . A method for forming a contact for a semiconductor device, comprising: 
 forming a first interlevel dielectric (ILD) layer on a conductive region;    etching the first ILD layer to form a first contact hole therein to expose the conductive region; and    filling the first contact hole with a porous layer having a high etch selectivity with respect to the first ILD layer to form a porous plug therein.    
     
     
         52 . The method of claim  51 , further comprising: 
 forming a second ILD layer overlying the porous plug;    etching the second ILD layer to form a second contact hole therein to expose the porous plug;    removing the porous plug in the first contact hole; and    filling the first and second contact holes with a conductive material to form a contact plug.