Trans-admittance trans-impedance logic for integrated circuits

Abstract

A logic circuit with improved performance when operating at the limits of the transistor's bandwidth. In particular, a latch includes a clocked trans-admittance stage circuit for receiving a voltage and producing a current output, and an active load, such as a trans-impedance stage circuit, connected to receive as input the current output of the trans-admittance stage circuit and produce a voltage input to the trans-admittance stage. The circuit output is taken from the output of the trans-admittance stage. Two independent trans-admittance and trans-impedance stages may be combined as a single latch pair. One or more latch pairs may be arranged in series as a cascaded chain and connected to the output current of a clocked trans-admittance stage latch to form a register.

What is claimed is:  
     
         1 . A latch comprising: 
 a clocked trans-admittance stage circuit for receiving a voltage on an input and producing a current output; and    an active load connected to receive a current on an input and produces a voltage output delivered to the input of the trans-admittance stage, the input of the active load being the input of the latch and the output of the trans-admittance stage being the output of the latch.    
     
     
         2 . The latch in accordance with  claim 1 , wherein the active load is a trans-impedance stage circuit.  
     
     
         3 . The latch in accordance with  claim 1 , wherein said trans-admittance stage circuit comprises: 
 a first pair of transistors including a first transistor and a second transistor;    a current source connected to the emitter of each of said first and second transistors;    a second pair of transistors including a third transistor and a fourth transistor, the emitter of each of said third and fourth transistors being connected to the collector of said first transistor; and    a third pair of transistors including a fifth transistor and a sixth transistor, the emitter of each of said fifth and sixth transistors being connected to the collector of said second transistor.    
     
     
         4 . The latch in accordance with  claim 2 , wherein said trans-impedance stage circuit comprises: 
 a fourth pair of transistors including seventh and eighth transistors with their emitters and collectors connected together, the collector of fifth transistor of the trans-admittance stage bing connected to the base of the seventh transistor of the trans-impedance stage and the collector of the sixth transistor of the trans-admittance stage being connected to the base of the eighth transistor of the trans-impedance stage, the latch output being taken from the collectors of the fifth and sixth transistors, and the input being to the bases of the seventh and eighth transistors.    
     
     
         5 . The latch in accordance with  claim 4 , wherein said trans-impedance stage circuit further comprises a fifth pair of transistors including ninth and tenth transistors, wherein said ninth and tenth transistors are connected as emitter followers for the seventh and eighth transistors respectively.  
     
     
         6 . The latch in accordance with  claim 3 , wherein the base of said first and second transmitters are clocked on opposite phases of a clock signal.  
     
     
         7 . The latch in accordance with  claim 6 , wherein the base of said third transistor receives as an input a voltage signal and the base of said fourth transistor receives as an input an inverted voltage signal, said third transistor produces a current output signal based on the inverted voltage signal, and said fourth transistor produces an inverted current output signal based on the voltage signal.  
     
     
         8 . The latch in accordance with  claim 1 , further comprising transmission lines coupled between said clocked trans-admittance circuit and said active load.  
     
     
         9 . A cascaded latch chain comprising: 
 a first stage with a clocked trans-admittance stage latch receiving an input voltage and producing an output current; and    a second stage with a trans-impedance stage receiving the output current of the trans-admittance stage latch of said first stage.    
     
     
         10 . The cascaded latch in accordance with  claim 9 , wherein said second stage is at least one trans-admittance stage—trans-impedance stage latch pair connected to receive the output current of said clocked trans-admittance stage latch of said first stage and producing an output current, said at least one latch pair including two independent combined trans-admittance and trans-impedance stages.  
     
     
         11 . The cascaded latch chain in accordance with  claim 10 , comprising at least two latch pairs including a first latch pair and a last latch pair, each latch pair having two independent trans-admittance and trans-impedance stages, the two trans-admittance and trans-impedance stages of each latch pair being clocked on opposite phases of a clock signal.  
     
     
         12 . The cascaded latch chain in accordance with  claim 11 , wherein said trans-admittance stage in each latch pair comprises: 
 a first pair of transistors including a first transistor and a second transistor,;    a current source connected to the emitter of each of said first and second transistors;    a second pair of transistors including a third transistor and a fourth transistor, the emitter of each of said third and fourth transistors being connected to the collector of said first transistor; and    a third pair of transistors including a fifth transistor and a sixth transistor, the emitter of each of said fifth and sixth transistors being connected to the collector of said second transistor.    
     
     
         13 . The cascaded latch chain in accordance with  claim 11 , wherein the two trans-admittance and trans-impedance stages in said at least one latch pair are clocked on opposite phases of a clock signal.  
     
     
         14 . The cascaded latch chain in accordance with  claim 9 , further comprising a trans-impedance stage latch connected to receive the output current of the last latch pair and produce an output voltage.  
     
     
         15 . The cascaded latch chain in accordance with  claim 10 , further comprising a trans-impedance stage latch connected to receive the output current of the last latch pair and produce an output voltage.  
     
     
         16 . A latch pair comprising: 
 two independent combined trans-admittance and trans-impedance stages.    
     
     
         17 . The latch pair in accordance with  claim 16 , wherein each trans-admittance stage comprises: 
 a first pair of transistors including a first transistor and a second transistor;    a current source connected to the emitter of each of said first and second transistors;    a second pair of transistors including a third transistor and a fourth transistor, the emitter of each of said third and fourth transistors being connected to the collector of said first transistor; and    a third pair of transistors including a fifth transistor and a sixth transistor, the emitter of each of said fifth and sixth transistors being connected to the collector of said second transistor.    
     
     
         18 . The latch in accordance with  claim 17 , wherein said trans-admittance stage circuit comprises: 
 a first pair of transistors including a first transistor and a second transistor;    a current source connected to the emitter of each of said first and second transistors;    a second pair of transistors including a third transistor and a fourth transistor, the emitter of each of said third and fourth transistors being connected to the collector of said first transistor; and    a third pair of transistors including a fifth transistor and a sixth transistor, the emitter of each of said fifth and sixth transistors being connected to the collector of said second transistor.    
     
     
         19 . The latch pair in accordance with  claim 17 , wherein the two trans-admittance and trans-impedance stages are clocked on opposite phases of a clock signal.