Semiconductor device for low voltage protection with low capacitance

Abstract

A semiconductor thyristor device ( 110 ) that incorporates buried regions ( 112 ) spaced around an emitter region ( 114 ). By spacing the buried regions ( 112 ) around the emitter region ( 114 ), current carriers emitted from the buried regions are distributed over a large area of the emitter region ( 114 ), thereby providing a high current capability during initial turn on of the device. In order to achieve low breakover voltage devices, the buried regions ( 112 ) are offset laterally with respect to the respective emitter regions ( 114 ). The low voltage thyristor device exhibits a low capacitance for operating with high speed, low voltage signals. The device capacitance is reduced by utilizing a plurality of buried regions ( 112 ), each formed having a relatively small area junction with the base region ( 118 ).

What is claimed is:  
     
         1 . A bidirectional overvoltage protection device, comprising: 
 a first group of semiconductor regions formed in a semiconductor chip for carrying current in response to a positive polarity voltage applied across the device;    a second group of semiconductor regions formed in the semiconductor chip for carrying current in response to a negative polarity voltage applied across the device; and    at least one buried region formed in association with each said first and second group of semiconductor regions, said buried regions being formed to define a breakover voltage for said overvoltage protection device, and formed centrally and laterally between two opposite sides of said semiconductor chip.    
     
     
         2 . The bidirectional overvoltage protection device of  claim 1 , further including an emitter region associated with each said first and second group of semiconductor regions, and wherein said buried regions are formed laterally offset from the respective emitter regions.  
     
     
         3 . The bidirectional overvoltage protection device of  claim 1  or  2 , wherein said semiconductor chip is formed with an anode and cathode contact for said first group of semiconductor regions, and a different anode and cathode contact for said second group of semiconductor regions.  
     
     
         4 . The bidirectional overvoltage protection device of  claim 3 , wherein said semiconductor chip is formed having an anode and contact cathode on one surface thereof, and the different anode and contact cathode on an opposite side surface of the semiconductor chip.  
     
     
         5 . The bidirectional overvoltage protection device of  claim 4 , wherein the anode and cathode contacts on one side of said semiconductor chip define different contacts that are short circuited together by a lead frame.  
     
     
         6 . The bidirectional overvoltage protection device of  claim 3 , further including in combination atop lead frame soldered to a top pair of contacts defining a first set of anode and cathode contacts, and a bottom lead frame soldered to a pair of contacts defining a second set of anode and cathode contacts.  
     
     
         7 . The bidirectional overvoltage protection device of  claim 1 ,  2  or  3 , wherein there is formed in one surface of said semiconductor chip at least one first base region and said emitter formed thereover, at least one second base region laterally spaced from said first base region, and a buried region formed between said first and second base regions.  
     
     
         8 . The bidirectional overvoltage protection device of  claim 7 , further including a PN junction between said buried region and said second base region, and including an electrically isolating material formed down into said junction to prevent current flow between said buried region and said second base region.  
     
     
         9 . The bidirectional overvoltage protection device of  claim 1 , wherein said second group of semiconductor regions are formed substantially identical to said first group of semiconductor regions, said first and second groups of semiconductor regions being formed in opposite faces of said semiconductor chip.  
     
     
         10 . The bidirectional overvoltage protection device of  claim 7 , further including a first metal contact electrically connected to said emitter, and a second metal contact electrically connected to said first base region, said first and second metal contacts being of substantially the same area when viewed from a top view.  
     
     
         11 . The bidirectional overvoltage protection device of  claim 1  or  2 , further including: 
 a buried region formed in one surface of said semiconductor chip, and a second buried region formed in an opposing surface of said semiconductor chip, and wherein said first and second buried regions are formed vertically aligned with each other.  
 
     
     
         12 . An overvoltage protection device, comprising: 
 at least one base region formed in a semiconductor material;    an emitter region formed in said base region such that abase-emitter junction is formed, said emitter region defined by a peripheral lateral boundary;    a plurality of buried regions for promoting current flow through said device during turn on, said buried regions formed with a breakdown junction for establishing a breakover voltage of said device; and    at least a portion of said buried regions each being laterally offset from said emitter region.    
     
     
         13 . The overvoltage protection device of  claim 12 , wherein said buried regions include buried regions spaced around the peripheral lateral boundary of said emitter region so that carriers emitted from said buried regions are collected by substantially an entire surface of said emitter region.  
     
     
         14 . The overvoltage protection device of  claim 12  or  13 , wherein said emitter region includes at least one opening therein, said opening bounded by a circular edge, and one said buried region is axially registered with said opening in said emitter region.  
     
     
         15 . The overvoltage protection device of  claim 12  or  13 , wherein said emitter region is formed with at least two comers, and further including at least two said buried regions formed laterally adjacent respective said comers of said emitter region.  
     
     
         16 . The overvoltage protection device of  claim 12 ,  13  or  14 , wherein said buried regions are formed using a mask having generally circular openings therein such that said buried regions have a generally circular profile.  
     
     
         17 . The overvoltage protection device of  claim 12 ,  13 ,  14 ,  15  or  16 , wherein said emitter region is formed with at least one indented area formed laterally in said peripheral boundary, and one said buried region is located so as to be laterally adjacent said indented area.  
     
     
         18 . The overvoltage protection device of  claim 14 , wherein said indented area has a shape substantially the same as a shape of a portion of said buried region located adjacent thereto.  
     
     
         19 . The overvoltage protection device of  claim 12 , further including an electrical isolation disposed between at least a portion of said base region and one said buried region to prevent current flow between a portion of said base region and said buried region.  
     
     
         20 . The overvoltage protection device of  claim 19 , wherein said electrical isolation comprises a trench formed in said base region and filled with an electrical insulating material.  
     
     
         21 . The overvoltage protection device of  claim 12 , wherein said base region comprises a first base region having an impurity concentration of a specified level having an impurity concentration greater than that of said first base region.  
     
     
         22 . The overvoltage protection device of  claim 21 , wherein said first base region is formed having a well with a lateral shape that is generally the same as a lateral shape of said emitter region.  
     
     
         23 . The overvoltage protection device of  claim 12 , further including an electrical isolation isolating at least a portion of one said buried region from at least a portion of said base region.  
     
     
         24 . An overvoltage protection device, comprising: 
 at least one base region formed in a semiconductor material;    an emitter region formed in said base region such that abase-emitter junction is formed, said emitter region having at least one opening therein bounded by a closed peripheral edge;    at least one buried region forming a breakdown junction with said base region, said breakdown junction being axially registered within said opening in said emitter region, and said breakdown junction being laterally offset from said closed peripheral edge.    
     
     
         25 . The overvoltage protection device of  claim 24 , further including plural said openings, and further including a plurality of said buried regions, each buried region having a breakdown junction axially aligned and laterally offset with a respective said emitter opening.