Method and apparatus for independent readout and reset of pixels within a CMOS image sensor

Abstract

A method of increasing the flexibility of the read out and reset functions of a CMOS image sensor is disclosed. This architecture allows new and unique modes of operation. These include the ability to read out and reset the pixels within a row simultaneously, for maximum exposure time, and the ability to reset a selected pixel or a selected group of pixels independently, without resetting any other pixels within the array, allowing the exposure time to be different than the frame time. Also allowing integration time to be unique for every pixel I the array

What is claimed:  
     
         1 . An imager comprising: 
 (a) a plurality of photosensitive elements, each element having a readout selection switch connected to a readout terminal, and a first reset selection switch connected to a reset terminal, separate from the readout terminal;    (b) an addressable selection circuit connected to the reset terminal;    (c) a separately addressable readout circuit connected to the readout terminal, so that a first photosensitive element can be selected for readout and a second photosensitive element can be selected for reset simultaneously.    
     
     
         2 . The imager of  claim 1 , further comprising a second reset selection switch in series circuit relationship with the first reset selection switch, and a second, separately addressable circuit connected to the second reset switch.  
     
     
         3 . The imager of  claim 1 , further comprising a second readout selection switch in series circuit relationship with the first readout selection switch, and a second, separately addressable circuit connected to the second readout switch.  
     
     
         4 . The imager of  claim 1 , further comprising a latch circuit for storing address information.  
     
     
         5 . The imager of  claim 1 , further comprising a plurality of unitary, differential-input, amplifiers, each amplifier having a plurality of first input transistors, one first input transistor located at each element within the periphery.  
     
     
         6 . The imager of  claim 5 , where the plurality of photosensitive elements are located within a periphery.  
     
     
         7 . The imager of  claim 6 , where each amplifier further comprises a second input transistor located outside the periphery of the array and connected to the first input transistors so as to create a feedback loop.