Data processing system and microcomputer

Abstract

An input/output device used as a transfer request source outputs a data transfer set command for specifying each transfer channel, each transfer address, the number of transfers, etc., onto a bus together with a data transfer request without involving use of the CPU. According to the data transfer set command, data transfer control information is set to direct memory access control means, and DMA transfer is started between the input/output device and a memory designated by the transfer address, for example. When the input/output device used as a data transfer request source desires to perform data transfer without regard to the state of processing by the microcomputer, it can perform data transfer processing with its own timing and the data transfer with the input/output device as a principal base is allowed.

What is claimed is:  
     
         1 . A microcomputer, comprising: 
 a central processing unit;    a direct memory access controller including a register to which control information used upon a data transfer operation is set, said direct memory access controller executing the data transfer operation in accordance with the control information set to said register;    a plurality of buses which include at least a first bus connected to said central processing unit and said direct memory access controller and a second bus connected to outside of the microcomputer;    a bus controller connected to said central processing unit, arbitrating a bus right of the first bus and second bus depending on receiving a bus request supplied from said central processing unit or said outside of microcomputer and giving said bus right to said central processing unit or outside of the microcomputer,    wherein control information is supplied to said bus connected to said register of said direct memory access controller from one of said central processing unit or outside of the microcomputer given said bus right, and    wherein said control information includes information to control the data transfer using the direct memory access controller.    
     
     
         2 . The microcomputer according to  claim 1 , wherein said outside of the microcomputer is able to get the control information to the register of said direct memory access controller via second bus.  
     
     
         3 . The microcomputer according to  claim 1 , wherein said central processing unit is able to set the control information to the register of said direct memory access controller via said first bus.  
     
     
         4 . The microcomputer according to  claim 2 , wherein the control information set to said register includes transfer source address information indicative of a transfer source of the data transfer operation or transfer destination address information indicative of a transfer destination of the data transfer operation.  
     
     
         5 . The microcomputer according to  claim 4 , wherein said direct memory access controller includes a plurality of data transfer channels, said register includes a plurality of registers respectively corresponding to said plurality of data transfer channels, and said registers are assigned to mutually different addresses by said central processing unit thereby the corresponding register assigned to the specified address by said central processing unit are set with control information to specify each address.  
     
     
         6 . The microcomputer according to  claim 5 , wherein the control information supplied to said bus includes information for specifying one of said plurality of data transfer channels, and the transfer source address information or the transfer destination address information is set to the register corresponding to the data transfer channel specified by the specifying information.  
     
     
         7 . A device connected to a bus which is able to connect to a semiconductor device including a bus controller and a data transfer controller and which functions as a data transfer source or a data transfer destination of a data transfer operation, said device comprising: 
 a processor implementing a predetermined function;    a controller outputting a bus request to said bus controller of said semiconductor device via said bus and outputting a data transfer request in response to approval of the bus request; and    an output unit outputting control information used upon the data transfer operation in synchronism with the output of the data transfer request to said data transfer controller of said semiconductor device via said bus.    
     
     
         8 . The device according to  claim 7 , wherein said control information includes address information for a transfer destination to transfer data according to the data transfer operation or address information indicative of an address for a transfer source in which each data to be transferred is stored.  
     
     
         9 . The device according to  claim 8 , wherein said processor, said controller and said output unit are formed on one semiconductor chip.  
     
     
         10 . The device according to  claim 8 , wherein said device is formed by a plurality of semiconductor chips.  
     
     
         11 . A data processing apparatus, comprising: 
 a microcomputer;    a bus coupled to said microcomputer; and    a device coupled to said bus,    wherein said microcomputer comprises:    a central processing unit coupled to said bus,    a direct memory access controller coupled to said bus including at least one register to which control information used upon a data transfer operation is set, said direct memory access controller executing the data transfer operation in accordance with the control information set to said register,    a bus controller connected to said central processing unit, receiving a use request of said bus from the outside of said microcomputer and a use request of said bus from said central processing unit and thereby being able to arbitrate between the use requests of the bus from the outside of said microcomputer and the central processing unit, and    a control circuit setting control information supplied to said bus to said register of said direct memory access controller when said bus controller acknowledges a bus use request from the outside; and    wherein said device comprises:    a processor implementing a predetermined function,    a controller outputting a use request related to said bus and outputting a data transfer request in response to approval of the use request, and    an output unit outputting the control information for the data transfer operation in synchronism with the output of the data transfer request.    
     
     
         12 . The data processing apparatus according to  claim 11 , wherein said control information includes address information for a transfer destination to transfer data according to the data transfer operation or address information indicative of an address for a transfer source in which each data to be transferred is stored.  
     
     
         13 . The data processing apparatus according to  claim 12 , wherein said control circuit sets the control information supplied to said bus to said register in response to a data transfer request to said direct memory access controller.