BIT line sense amplifier suppressing a pull-up voltage of a BIT signal and semiconductor memory device having the same

Abstract

A bit line sense amplifier suppressing a pull-up voltage of a bit signal and a semiconductor memory device having the same. The bit line sense amplifier includes an amplifying portion, a pull-up portion and a pull-down portion. The amplifying portion is disposed between a pull-up node and a pull-down node, and amplifies a bit signal and a complementary bit signal. The amplifying portion has two inverters cross-coupled as a latch. The pull-up portion is disposed between a power supply node and the pull-up node, and pulls up a voltage level of the pull-up node in response to a pull-up control signal. The pull-down portion is disposed between a ground voltage and the pull-down node and is controlled by a pull-down control signal. The pull-down portion pulls down a voltage level of the pull-down node. The pull-up portion includes a first transistor and a second transistor. The first transistor drops a voltage level of the power supply node by a predetermined voltage level. The second transistor provides a voltage of the power supply node dropped by the first transistor to the pull-up node. In the NMOS pull-up type bit line sense amplifier according to the present invention, the pull-up voltage of the pull-up node is limited to (VDD-Vt) and a maximum pull-up voltage of the bit signal is also limited to (VDD-Vt). Therefore, the semiconductor memory device having the bit line sense amplifier in the invention can prevent excessive current consumption and stress.

What is claimed is:  
     
         1 . A semiconductor memory device, comprising: 
 a bit line sense amplifier for sensing a bit signal and a complementary bit signal, and amplifying the bit signal and the complementary bit signal; and    a memory cell for storing the bit signal,    wherein the memory cell includes: 
 an NMOS transfer transistor, which is controlled by a word signal, for transferring the bit signal; and  
 a capacitor for storing the bit signal transferred by the NMOS transfer transistor,  
   wherein the bit line sense amplifier includes: 
 an amplifying portion for amplifying the bit signal and the complementary bit signal, the amplifying portion being disposed between a pull-up node and a pull-down node, and having two inverters cross-coupled as a latch;  
 a pull-up portion for pulling up a voltage level of the pull-up node, the pull-up portion being disposed between a power supply node and the pull-up node, having a first NMOS transistor, and being controlled by a control signal; and  
 a pull-down portion for pulling down a voltage level of the pull-down node, the pull-down portion being disposed between a ground voltage and the pull-down node, having a second NMOS transistor, and being controlled by the control signal,  
   wherein the word signal and the control signal are activated with a voltage level substantially equal to that of the power supply node.    
     
     
         2 . The semiconductor memory device in accordance with  claim 1 , wherein the voltage of the power supply node is an external power voltage.  
     
     
         3 . The semiconductor memory device in accordance with  claim 1 , wherein the first NMOS transistor includes a source coupled to the pull-up node, a drain coupled to the power supply node and a gate controlled by the control signal, and 
 wherein the second NMOS transistor includes a source coupled to the ground voltage, a drain coupled to the pull-down node and a gate controlled by the control signal.    
     
     
         4 . The semiconductor memory device in accordance with  claim 1 , wherein a threshold voltage of the first NMOS transistor is substantially equal to or less than that of the NMOS transfer transistor.  
     
     
         5 . The semiconductor memory device in accordance with  claim 1 , wherein the capacitor is formed with a third NMOS transistor.  
     
     
         6 . A semiconductor memory device, comprising: 
 a bit line sense amplifier for sensing a bit signal and a complementary bit signal, and amplifying the bit signal and the complementary bit signal; and    a memory cell for storing the bit signal,    wherein the memory cell includes: 
 an NMOS transfer transistor, which is controlled by a word signal, for transferring the bit signal; and  
 a capacitor for storing the bit signal transferred by the NMOS transfer transistor,  
   wherein the bit line sense amplifier includes: 
 an amplifying portion for amplifying the bit signal and the complementary bit signal, the amplifying portion being disposed between a pull-up node and a pull-down node, and having two inverters cross-coupled as a latch;  
 a pull-up portion for pulling up a voltage level of the pull-up node, the pull-up portion being disposed between a power supply node and the pull-up node, having a first NMOS transistor, and being controlled by a pull-up control signal; and  
 a pull-down portion for pulling down a voltage level of the pull-down node, the pull-down portion being disposed between a ground voltage and the pull-down node, having a second NMOS transistor, and being controlled by a pull-down control signal,  
   wherein the pull-up control signal is activated before the pull-down control signal, in order that the first NMOS transistor is controlled together with the second NMOS transistor simultaneously.    
     
     
         7 . The semiconductor memory device in accordance with  claim 6 , wherein the pull-up control signal, the pull-down control signal and the word signal are activated to a voltage level substantially equal to the voltage level of the power supply node.  
     
     
         8 . The semiconductor memory device in accordance with  claim 7 , wherein the voltage of the power supply node is an external power voltage.  
     
     
         9 . The semiconductor memory device in accordance with  claim 6 , wherein the first NMOS transistor has a source coupled to the pull-up node, a drain coupled to the power supply node and a gate controlled by the pull-up control signal, and 
 wherein the second NMOS transistor has a source coupled to the ground voltage, a drain coupled to the pull-down node and a gate controlled by the pull-down control signal.    
     
     
         10 . The semiconductor memory device in accordance with  claim 6 , wherein a threshold voltage of the first NMOS transistor is substantially equal to or less than that of the NMOS transfer transistor.  
     
     
         11 . The semiconductor memory device in accordance with  claim 6 , wherein the capacitor is formed with a third NMOS transistor.  
     
     
         12 . A bit line sense amplifier for a semiconductor memory device, comprising: 
 an amplifying portion for amplifying a bit signal and a complementary bit signal, the amplifying portion being disposed between a pull-up node and a pull-down node, and having two inverters cross-coupled as a latch;    a pull-up portion for pulling up a voltage level of the pull-up node, the pull-up portion being disposed between a power supply node and the pull-up node, having a first NMOS transistor, and being controlled by a pull-up control signal; and    a pull-down portion for pulling down a voltage level of the pull-down node, the pull-down portion being disposed between a ground voltage and the pull-down node, having a second NMOS transistor, and being controlled by a pull-down control signal,    wherein the pull-up control signal is activated before the pull-down control signal, in order that the first NMOS transistor is controlled together with the second NMOS transistor simultaneously.    
     
     
         13 . A bit line sense amplifier for a semiconductor memory device, comprising: 
 an amplifying portion for amplifying a bit signal and a complementary bit signal, the amplifying portion being disposed between a pull-up node and a pull-down node, and having two inverters cross-coupled as a latch;    a pull-up portion for pulling up a voltage level of the pull-up node in response to a pull-up control signal, the pull-up portion being disposed between a power supply node and the pull-up node; and    a pull-down portion for pulling down a voltage level of the pull-down node, the pull-down portion being disposed between a ground voltage and the pull-down node, and being controlled by a pull-down control signal,    wherein the pull-up portion includes a first transistor for dropping a voltage level of the power supply node by a predetermined voltage level; and a second transistor for providing a voltage of the power supply node dropped by the first transistor to the pull-up node.    
     
     
         14 . The bit line sense amplifier in accordance with  claim 13 , wherein the first transistor is formed with an NMOS transistor.  
     
     
         15 . A semiconductor memory device, comprising: 
 a bit line sense amplifier for sensing and amplifying a bit signal and a complementary bit signal; and    a memory cell for storing the bit signal,    wherein the memory cell includes: 
 an NMOS transfer transistor, which is controlled by a word signal, transferring the bit signal; and  
 a capacitor for storing the bit signal transferred by the NMOS transfer transistor,  
   wherein the bit line sense amplifier includes: 
 an amplifying portion for amplifying the bit signal and the complementary bit signal, the amplifying portion being disposed between a pull-up node and a pull-down node, and having two inverters cross-coupled as a latch;  
 a pull-up portion for pulling up a voltage level of the pull-up node, the pull-up portion being disposed between a power supply node and the pull-up node, and being controlled by a control signal and; and  
 a pull-down portion for pulling down a voltage level of the pull-down node, the pull-down portion being disposed between a ground voltage and the pull-down node, and being controlled by the control and,  
   wherein the pull-up portion further includes: 
 a first transistor for dropping a voltage level of the power supply node by a predetermined voltage level; and  
 a second transistor for providing a voltage of the power supply node dropped by the first transistor to the pull-up node, gated by a pull-up control signal.  
   
     
     
         16 . The semiconductor memory device in accordance with  claim 15 , wherein the first transistor is formed with an NMOS transistor.  
     
     
         17 . The semiconductor memory device in accordance with  claim 15 , wherein the voltage of the power supply node is an external power voltage.  
     
     
         18 . The semiconductor memory device in accordance with  claim 15 , wherein a threshold voltage of the first transistor is substantially equal to or less than that of the NMOS transfer transistor.  
     
     
         19 . The semiconductor memory device in accordance with  claim 15 , wherein the capacitor is formed with a third NMOS transistor.