Integrated circuit with stop layer and method of manufacturing the same

Abstract

A method of manufacturing an integrated circuit is provided. According to the method, first and second stop layers are deposited on a first dielectric layer that covers a first metallization level. The second stop layer is selectively etched with respect to the first stop layer, and the first stop layer is selectively etched with respect to the first dielectric layer. A second dielectric layer and a third stop layer are deposited. The third stop layer is selectively etched with respect to the second dielectric layer, and the first and second dielectric layers are selectively etched with respect to the stop layers so as to form trenches in the second dielectric layer and holes in the first dielectric layer. Additionally, an integrated circuit is provided that includes first and second metallization levels. A dielectric layer is located between the metallization levels, and a first stop layer is located between the dielectric layer and the second metallization level. A second stop layer is located above the first stop layer, and a third stop layer is located above the dielectric material of the second metallization level. In one preferred embodiment, lines of at least one metallization levels are made of copper, and the dielectric layer is made of an organic polymer having an electrical permittivity coefficient of less than 3.

What is claimed is:  
     
         1 . A method of manufacturing an integrated circuit, said method comprising the steps of: 
 depositing first and second stop layers on a first dielectric layer that covers a first metallization level;    selectively etching the second stop layer with respect to the first stop layer;    selectively etching the first stop layer with respect to the first dielectric layer;    depositing a second dielectric layer on the circuit, and    selectively etching the first and second dielectric layers with respect to the stop layers so as to form trenches in the second dielectric layer and holes in the first dielectric layer.    
     
     
         2 . The method as defined in  claim 1 , further comprising the steps of: 
 depositing a third stop layer on the second dielectric layer;    selectively etching the third stop layer with respect to the second dielectric layer;    
     
     
         3 . The method as defined in  claim 1 , further comprising the steps of: 
 after depositing the first and second stop layers, depositing a first mask on the second stop layer; and    after depositing the third stop layer, depositing a second mask on the third stop layer.    
     
     
         4 . The method as defined in  claim 3 , wherein in the step of selectively etching the first and second dielectric layers, the second mask is removed simultaneously with the forming of the trenches and holes.  
     
     
         5 . The method as defined in  claim 3 , wherein the first and second masks are resin masks.  
     
     
         6 . The method as defined in  claim 1 , further comprising the step of depositing metal in the holes and trenches to form a second metallization level and vias connecting the first and second metallization levels.  
     
     
         7 . The method as defined in  claim 6 , wherein each of the first and second metallization levels includes metallization lines separated by dielectric material.  
     
     
         8 . The method as defined in  claim 7 , further comprising the step of etching a layer for encapsulating the metallization lines of the second metallization level.  
     
     
         9 . The method as defined in  claim 1 , further comprising the step of etching a layer for encapsulating lines of a second metallization level.  
     
     
         10 . An integrated circuit comprising: 
 at least first and second metallization levels, each of the metallization levels including metallization lines separated by dielectric material;    a dielectric layer located between the first and second metallization levels, the dielectric layer being penetrated by vias that electrically connect the metallization lines of the first and second metallization levels;    a first stop layer located between the dielectric layer and the second metallization level, the first stop layer being selectively etchable with respect to the dielectric layer; and    a second stop layer located above the first stop layer, the second stop layer being selectively etchable with respect to the first stop layer.    
     
     
         11 . The integrated circuit as defined in  claim 10 , further comprising 
 a third stop layer located above the dielectric material of the second metallization level, the third stop layer being selectively etchable with respect to the dielectric material of the second metallization level.    
     
     
         12 . The integrated circuit as defined in  claim 10 , wherein the metallization lines of at least one of the first and second metallization levels are made of copper.  
     
     
         13 . The integrated circuit as defined in  claim 11 , wherein the dielectric layer is made of an organic polymer having an electrical permittivity coefficient of less than 3.  
     
     
         14 . The integrated circuit as defined in  claim 10 , wherein the dielectric layer is made of an organic polymer having an electrical permittivity coefficient of less than 3.  
     
     
         15 . The integrated circuit as defined in  claim 10 , wherein the dielectric material of the first and second metallization levels is the same as the material of the dielectric layer.  
     
     
         16 . The integrated circuit as defined in  claim 10 , wherein the first stop layer is made of silicon nitride.  
     
     
         17 . The integrated circuit as defined in  claim 15 , wherein the second stop layer is made of silicon oxide.  
     
     
         18 . The integrated circuit as defined in  claim 15 , wherein the second stop layer is made of silicon oxynitride.  
     
     
         19 . The integrated circuit as defined in  claim 10 , wherein the first stop layer is made of silicon oxynitride.  
     
     
         20 . The integrated circuit as defined in  claim 18 , wherein the second stop layer is made of silicon oxide.  
     
     
         21 . The integrated circuit as defined in  claim 10 , wherein the second stop layer is made of silicon oxide.  
     
     
         22 . The integrated circuit as defined in  claim 10 , wherein the third stop layer is made of silicon nitride, silicon oxide, or silicon oxynitride.  
     
     
         23 . The integrated circuit as defined in  claim 10 , further comprising a layer for encapsulating the metallization lines of the second metallization level.  
     
     
         24 . An information handling system including at least one semiconductor device that contains an integrated circuit, said integrated circuit comprising: 
 at least first and second metallization levels, each of the metallization levels including metallization lines separated by dielectric material;    a dielectric layer located between the first and second metallization levels, the dielectric layer being penetrated by vias that electrically connect the metallization lines of the first and second metallization levels;    a first stop layer located between the dielectric layer and the second metallization level, the first stop layer being selectively etchable with respect to the dielectric layer; and    a second stop layer located above the first stop layer, the second stop layer being selectively etchable with respect to the first stop layer.    
     
     
         25 . The information handling system as defined in  claim 24 , further comprising 
 a third stop layer located above the dielectric material of the second metallization level, the third stop layer being selectively etchable with respect to the dielectric material of the second metallization level.    
     
     
         26 . The information handling system as defined in  claim 24 , wherein the metallization lines of at least one of the first and second metallization levels are made of copper.  
     
     
         27 . The information handling system as defined in  claim 24 , wherein the dielectric layer is made of an organic polymer having an electrical permittivity coefficient of less than 3.