Integrated radio frequency circuits

Abstract

An RF circuit may be formed over a triple well that creates two reverse biased junctions. By adjusting the bias across the junctions, the capacitance across the junctions can be reduced, reducing the capacitive coupling from the RF circuits to the substrate, improving the self-resonance frequency of inductors and reducing the coupling of unwanted signals and noise from the underlying substrate to the active circuits and passive components such as the capacitors and inductors. As a result, radio frequency devices, such as radios, cellular telephones and transceivers such as Bluetooth transceivers, logic devices and Flash and SRAM memory devices may all be formed in the same integrated circuit die using CMOS fabrication processes.

What is claimed is:  
     
         1 . A method comprising: 
 forming the common gate transistor of a cascode circuit over a triple well in a substrate; and    biasing a well of said triple well through a resistor.    
     
     
         2 . The method of  claim 1  including forming an integrated inductor over a triple well.  
     
     
         3 . The method of  claim 1  including forming a P-type well in an N-type well formed in said substrate.  
     
     
         4 . The method of  claim 3  including biasing the N-type and P-type wells through resistors.  
     
     
         5 . The method of  claim 1  including coupling the source of said common gate transistor to the source of another transistor.  
     
     
         6 . The method of  claim 5  including taking the output of said cascode circuit from the drain of said common gate transistor.  
     
     
         7 . The method of  claim 4  including biasing said regions to isolate the output of said cascode circuit from the substrate.  
     
     
         8 . The method of  claim 7  including reducing the output shunt capacitance using said triple well.  
     
     
         9 . An integrated circuit comprising: 
 a substrate;    a cascade circuit formed over said substrate; and    a triple well formed in said substrate under said cascode circuit.    
     
     
         10 . The circuit of  claim 9  wherein the cascode circuit includes a common gate transistor formed over said triple well.  
     
     
         11 . The circuit of  claim 10  wherein the triple well each includes a P-well formed in an N-well formed in the substrate.  
     
     
         12 . The circuit of  claim 11  including resistors coupled to said wells, said resistors being coupled to bias potentials.  
     
     
         13 . The circuit of  claim 12  including a transistor coupled to the source of said common gate transistor.  
     
     
         14 . The circuit of  claim 13  including an output node coupled tc the drain of said common gate transistor.  
     
     
         15 . The circuit of  claim 14  wherein said wells are biased to isolate said output node and said substrate.