Container capacitor structure and method of formation thereof

Abstract

Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

What is claimed is:  
     
         1 . A method of fabricating a container capacitor comprising: 
 forming a conductive first electrode container well;    forming a capacitor structure within the well and on a predetermined portion of the exterior of the well, wherein the capacitor structure extends from the container well at two different levels, a first level substantially at the top of the container and a second level below the top of the container.    
     
     
         2 . The method of  claim 1 , wherein the first electrode container well is surrounded on its exterior by a supporting dielectric, and wherein forming the capacitor structure comprises: 
 forming recesses in the supporting dielectric to expose the predetermined exterior surface portion to the two different levels of supporting dielectric;    depositing a capacitor dielectric layer on the interior of the first electrode container well and on the exposed portion of the exterior surface of the first electrode container well; and    depositing a conductive top electrode over the capacitor dielectric layer, wherein the top electrode extends from the container at the two different levels.    
     
     
         3 . The method of  claim 1  wherein the two levels comprise a first level below the top surface of the container and a second level below the first level.  
     
     
         4 . The method of  claim 1  wherein the two levels are separated by a vertical spacing of at least 500 angstroms.  
     
     
         5 . The method of  claim 1  wherein the predetermined portion of the exterior of the well is askew from another capacitor structure.  
     
     
         6 . A method of forming an array of container capacitors comprising: 
 forming a plurality of spaced apart first electrode container wells; and    forming a capacitor structure within each of the container wells and on a predetermined portion of the exterior of each container well, wherein the predetermined portion comprises a portion of the exterior that is askew from an adjacent container well, and, wherein forming a capacitor structure on a predetermined portion of the exterior comprises, 
 forming a supporting dielectric on the exterior of the array of container wells to the top of the array of container wells, and  
 etching a portion of the supporting dielectric to a level below the top of the container wells.  
   
     
     
         7 . The method of  claim 6  wherein the level below the top of the container wells is at least 500 angstroms below the top of the container wells.  
     
     
         8 . The method of  claim 6  wherein forming a capacitor structure further comprises: 
 depositing a capacitor dielectric layer on each interior surface and each exposed portion of the exterior surface; and  
 depositing a top electrode on the capacitor dielectric layer; and  
 wherein the capacitor dielectric layer and the top electrode extend from the container wells at the at least two different levels.  
 
     
     
         9 . A method of fabricating a capacitor comprising: 
 depositing a capacitor first electrode container;    depositing a supporting dielectric around the exterior of the container, the supporting dielectric extending substantially to the top of the container exterior;    forming recesses in the supporting dielectric to expose surface portions of the exterior of the container at a level below the top of the container exterior;    depositing a capacitor dielectric layer on the interior surface and the exposed portion of the exterior surface; and    depositing a conductive top electrode on the capacitor dielectric layer.    
     
     
         10 . The method of  claim 9  wherein forming recesses comprises: 
 depositing an etch mask within boundaries of the exterior surface portion; and  
 removing the supporting dielectric not masked by the etch mask.  
 
     
     
         11 . The method of  claim 9  and further comprising: 
 forming a second capacitor adjacent the capacitor, and wherein the exposed surface portions of the first and the second capacitor face each other.  
 
     
     
         12 . A method of forming an array of capacitors comprising: 
 forming a plurality of capacitor first electrodes;    forming a plurality of access point areas overlaid by a supporting dielectric which also encases the capacitor first electrodes;    etching recesses to expose exterior portions of the capacitor first electrodes at a height different from the top of the supporting dielectric, each exposed exterior portion facing an adjacent first electrode;    forming a capacitor dielectric layer on each interior surface of the first electrodes and on each exposed exterior of the first electrodes; and    forming a second electrode on each capacitor dielectric layer.    
     
     
         13 . The method of  claim 12  wherein forming each capacitor dielectric layer further comprises forming the layer with at least two elevations at which each dielectric layer extends away from its respective first electrode bottom cup electrode and toward a contact site for an access transistor.  
     
     
         14 . A method of forming a container capacitor comprising: 
 exposing an interior surface and predetermined exterior portions of a supporting dielectric encased container bottom electrode, wherein the supporting dielectric contacts the entire vertical exterior surface of the container in one portion and less that the entire vertical exterior surface in another portion;    forming a capacitor dielectric layer over the exposed predetermined portions of the exterior of the container and of the interior of the container; and    forming a top electrode layer over the capacitor dielectric layer.    
     
     
         15 . The method of  claim 14  wherein exposing the predetermined exterior portions comprises selectively etching portions of the supporting dielectric to at least two different vertical levels of the container.  
     
     
         16 . The method of  claim 15  wherein the at least two levels are separated by a vertical distance of at least 500 angstroms.  
     
     
         17 . The method of  claim 14  wherein forming a capacitor dielectric layer and forming top electrode layer are performed at an upper location of the container capacitor.  
     
     
         18 . The method of  claim 14  wherein exposing predetermined portions of the exterior comprises forming recesses in the supporting dielectric.  
     
     
         19 . A method of forming a container capacitor array having a plurality of container capacitors and a plurality of access transistors, the method comprising: 
 forming the plurality of access transistors spaced apart from one another by the plurality of container capacitor cups; and    forming the plurality of container capacitors at the location of the container capacitor cups, wherein forming the plurality of container capacitors comprises: 
 planarizing the top of the array;  
 etching recesses between directly adjacent container wells to expose a predetermined portion of the exterior of each of the container wells, wherein the recesses expose the predetermined portion at at least two different levels of the container wells, the at least two different levels are a first level at the top of the container wells and a second level below the top of the container wells;  
 depositing a capacitor dielectric layer over the interior of the containers and in the recesses; and  
 forming a top electrode layer over the capacitor dielectric layer.  
   
     
     
         20 . The method of  claim 19  wherein the at least two different levels are a first level below the top of the container wells and a second level below the first level.  
     
     
         21 . The method of  claim 19  wherein depositing a capacitor dielectric layer and forming a top electrode layer are performed at an upper location of the container capacitor.  
     
     
         22 . The method of  claim 19  wherein depositing each capacitor dielectric layer further comprises depositing the layer with at least two elevations at which each dielectric layer extends away from its respective first electrode bottom cup electrode and toward a contact site for an access transistor.  
     
     
         23 . The method of  claim 22  wherein the first elevation is at a portion of the container well facing an adjacent container and the second elevation is at portion of the container well facing a contact point area.  
     
     
         24 . The method of  claim 19  and further comprising: 
 forming an access point contact area above each access transistor; and  
 wherein etching recesses is performed to expose a portion of the exterior surface not facing an access point contact area.  
 
     
     
         25 . The method of  claim 24  and further comprising: 
 forming a conductive plug at each access point to each access transistor.  
 
     
     
         26 . The method of  claim 25  wherein the conductive plug is formed by etching an opening in the top electrode and dielectric layer larger than the access point contact area, and depositing a conductive material in the opening.  
     
     
         27 . A method of forming a memory cell comprising: 
 forming a bottom electrode of a capacitor having a container shape with exterior and interior surfaces;    forming a substantially vertically extending bit line contact extending from a vertical height above the bottom electrode to a source/drain region of an access transistor;    forming an insulation region around the bit line contact abutting a portion of the exterior surface of the bottom electrode;    forming a dielectric layer over the interior surface and the exterior surface not abutting the insulation region; and    forming a top plate over the dielectric layer.    
     
     
         28 . A method of fabricating a capacitor array comprising: 
 forming a plurality of first electrodes each having a container shape with an interior surface and an exterior surface;    forming a plurality of access transistors, the access transistors each having an access point and the first electrodes spaced apart so that each access point is surrounded by a number of first electrodes;    forming a dielectric layer over each of the interior surfaces and a predetermined portion of each of the exterior surfaces, wherein forming the dielectric layer comprises: 
 depositing a supporting dielectric around each of the first electrodes extending to the top of each container,  
 etching predetermined portions of the supporting dielectric to a level below the top of each container to expose the predetermined portions of the exterior of each container, and  
 depositing a capacitor dielectric over each of the interior surfaces and the predetermined portion of each of the exterior surfaces; and  
   forming a second electrode over each of the dielectric layers.    
     
     
         29 . A method of forming a memory cell comprising: 
 forming an access transistor stack on a substrate;    forming a container capacitor bottom electrode adjacent the transistor stack;    supporting the container capacitor bottom electrode with a supporting dielectric encompassing the exterior surface of the bottom electrode and covering the access transistor stack;    removing a portion of the supporting dielectric to expose a portion of the exterior surface of the bottom electrode but not the access transistor stack;    depositing a capacitor dielectric on the interior surface of the bottom electrode and on the exposed portion of the exterior surface of the bottom electrode, the capacitor dielectric extending from the bottom electrode at two different levels; and    depositing a top electrode on the capacitor dielectric.    
     
     
         30 . The method of  claim 29  wherein removing a portion of the supporting dielectric comprises removing a portion not facing the access transistor stack.  
     
     
         31 . The method of  claim 29  wherein the two levels comprises a first level at the top of the container bottom electrode and a second level below the first level.  
     
     
         32 . The method of claim  31  wherein the first and the second levels are separated by a vertical distance of at least 500 angstroms.