Impurity ion segregation precluding layer, fabrication method thereof, isolation structure for semiconductor device using the impurity ion segregation precluding layer and fabricating method thereof

Abstract

The present invention relates to the impurity ion segregation precluding layer, the fabrication method thereof, the isolation structure for the semiconductor device using the segregation precluding layer and the fabrication method thereof, which are provided to prevent impurity ions from segregating into a device isolation region in a semiconductor substrate and eventually restrain decrease in a threshold voltage due to the segregation of impurity ion, particularly, boron ions in the semiconductor substrate. The isolation structure of the semiconductor device is fabricated by forming a trench in a portion of the semiconductor substrate; placing the semiconductor substrate into a high-temperature furnace; annealing the semiconductor substrate flowing a nitride gas at about 20 l/min into the furnace; and filling an insulator in the trench. Thus, an impurity ion segregation precluding film is formed on a surface of the trench at a thickness of 1-10A in the annealing process using the nitride gas, so that the decrease in the threshold voltage of the semiconductor device is restrained and thus the semiconductor device can stably operate.

What is claimed is:  
     
         1 . An impurity ion segregation precluding layer formed on a silicon substrate and having a thickness of 10A or less, said segregation precluding layer being obtained by placing the silicon substrate in a high-temperature furnace and annealing the silicon substrate while flowing a nitride gas at at least 20 l/min thereinto.  
     
     
         2 . The impurity ion segregation precluding layer according to  claim 1 , wherein the impurity ion segregation precluding layer is a nitrogen-rich silicon nitride.  
     
     
         3 . The impurity ion segregation precluding layer according to  claim 1 , wherein the annealing process is performed in the furnace at about 800□C.  
     
     
         4 . The impurity ion segregation precluding layer according to  claim 1 , wherein the impurity ion segregation precluding layer restrains oxidization of the silicon substrate.  
     
     
         5 . The impurity ion segregation precluding layer according to  claim 1 , wherein the impurity ion segregation precluding layer is not etched by a buffered oxide etchant (BOE).  
     
     
         6 . A method for fabricating an impurity ion segregation precluding layer, comprising the steps of: 
 preparing a silicon substrate and    placing the silicon substrate into a furnace at a high temperature and annealing the silicon substrate flowing a nitride gas at about 20 l/min into the furnace.    
     
     
         7 . The method according to  claim 6 , wherein the annealing process is performed in the furnace at about 800□C.  
     
     
         8 . The method according to  claim 6 , wherein the annealing process is performed to form a nitrogen-rich silicon nitride having a thickness of 10 A or less.  
     
     
         9 . An isolation structure of a semiconductor device, comprising: 
 a semiconductor substrate;    a trench formed in a predetermined portion of the semiconductor substrate;    an impurity ion segregation precluding layer formed on a surface of the trench; and    an insulator filled in the trench, the impurity ion segregation precluding layer being obtained by placing the semiconductor substrate into a furnace at a high temperature and annealing the semiconductor substrate flowing a nitride gas at about 20 l/min into the furnace.    
     
     
         10 . The isolation structure according to  claim 9 , wherein the impurity ion segregation precluding layer has a thickness of 10A or less.  
     
     
         11 . The isolation structure according to  claim 9 , wherein the insulator is a silicon oxide or a silicon nitride.  
     
     
         12 . The isolation structure according to  claim 9 , wherein the impurity ion segregation precluding layer is a nitrogen-rich silicon nitride.  
     
     
         13 . A method of fabricating an isolation structure of a semiconductor device, comprising the steps of: 
 preparing a semiconductor substrate;    forming a trench in a portion of the semiconductor substrate corresponding to a device isolation region;    forming a nitrogen-rich silicon nitride having a thickness of 10A or less on a surface of the trench; and    filling an insulator in the trench.    
     
     
         14 . A method of fabricating an isolation structure of a semiconductor device, comprising the steps of: 
 preparing a semiconductor substrate;    forming a trench in a portion of the semiconductor substrate corresponding to a device isolation region;    placing the semiconductor substrate into a furnace at a high temperature;    annealing the semiconductor substrate flowing a nitride gas at about 20 l/min into the furnace; and    filling an insulator in the trench.    
     
     
         15 . The method according to  claim 14 , wherein the annealing process is performed to form an impurity ion segregation precluding layer having a thickness of 10A or less on a sidewall and a bottom surface of the trench of the semiconductor substrate.  
     
     
         16 . The method according to  claim 15 , wherein the impurity ion segregation precluding layer is a nitrogen-rich silicon nitride.  
     
     
         17 . The method according to  claim 14 , further comprising the steps of: 
 after forming the trench, annealing the semiconductor substrate at a temperature of 1000-1050□C in an oxygen atmosphere, for thereby forming a thermal oxide on the surface of the trench, the thermal oxide having a thickness of 50-200A; and    removing the thermal oxide with an HF solution.    
     
     
         18 . The method according to  claim 14 , wherein the step of filling the insulator in the trench includes: 
 forming an insulating film over an entire surface of the semiconductor substrate which is obtained from the annealing process; and    planarizing the insulating film by a chemical mechanical polishing method, so that the insulating film only remains in the trench.    
     
     
         19 . The method according to  claim 14 , wherein the step of forming the trench includes: 
 forming a pad oxide on the semiconductor substrate;    forming a silicon nitride on the pad oxide;    forming a photoresist pattern on a portion of the silicon nitride corresponding to an active region; and    removing the silicon nitride and the pad oxide by using the photoresist pattern as a mask and etching the semiconductor substrate formed under the removed pad oxide to a predetermined depth.