Low voltage rail-to-rail CMOS output stage

Abstract

An output stage suitable for low voltage operation and capable of providing an essentially symmetrical rail-to-rail output voltage including a first field effect device having a first drain, a first gate, and a first source coupled to a power supply V CC . The output stage further includes a second field effect device complimentary to the first field effect device, having a second drain, a second gate, and a second source coupled to a power supply having a nominal voltage of V EE . Further, the second drain is coupled to the first drain. Further, the output stage is an output sink network coupled to the second field effect device. The output sink network drives the second field effect device such that a current is produced in the first field effect device and a current in the second field effect device is essentially equal to a predetermined constant during operation of the output stage.

What is claimed is:  
     
         1 . An output stage for providing a substantially symmetrical rail-to-rail output voltage, the output stage comprising: 
 a first field effect device having a first source, first drain, and first gate, the first source being coupled to a power supply V CC ;    a second field effect device complementary to the first field effect device, wherein the second field effect device includes a second source, second drain, and second gate, and wherein the second source is coupled to a power supply having a nominal voltage supply of V EE  and wherein the second drain is coupled to the first drain; and    an output sink network coupled to the second gate, wherein the output sink network drives the second field effect device such that a product of a first current in the first field effect device and a second current in the second field effect device is substantially equal to a predetermined constant.    
     
     
         2 . An output stage as recited in  claim 1 , wherein a sum of the first current and the second current is essentially equal to a predetermined constant during operation of the output stage.  
     
     
         3 . An output stage as recited in  claim 1 , wherein the first field effect device is configured in a common source configuration.  
     
     
         4 . An output stage as recited in  claim 1 , wherein the first field effect device is a P-channel metal oxide semiconductor field effect (PMOS) transistor.  
     
     
         5 . An output stage as recited in  claim 4 , wherein the second field effect device is an N-channel metal oxide semiconductor field effect (NMOS) transistor.  
     
     
         6 . An output stage as recited in  claim 5 , wherein the output sink network utilizes a current mirror to track the current in the first field effect device.  
     
     
         7 . An output stage as recited in  claim 6 , wherein the current mirror tracks the current in the first field effect device at a predetermined ratio of the current in the first field.  
     
     
         8 . An output stage as recited in  claim 1 , wherein the first field effect device is an N-channel metal oxide semiconductor field effect (NMOS) transistor.  
     
     
         9 . An output stage as recited in  claim 8 , wherein the second field effect device is a P-channel metal oxide semiconductor field effect (PMOS) transistor.  
     
     
         10 . An output stage as recited in  claim 1 , wherein a substantially rail-to-rail output voltage produced by the output stage is no more than one V GS  and two V Dsat  from either rail.  
     
     
         11 . A method for providing an output signal from an output stage of a low voltage operation amplifier capable of providing a substantially rail-to-rail output voltage, the method comprising the operations of: 
 providing an input signal to a first field effect device having a first source, first drain, and first gate, the first source being coupled to a power supply V CC ; and    driving a second complimentary field effect device utilizing an output sink network such that a product of a first current in the first field effect device and a second current in the second field effect device is substantially equal to a predetermined constant.    
     
     
         12 . A method as recited in  claim 11 , wherein a sum of the first current and the second current is essentially equal to a predetermined constant during operation of the amplifier.  
     
     
         13 . A method as recited in  claim 11 , wherein the first field effect device is configured in a common source configuration.  
     
     
         14 . A method as recited in  claim 13 , wherein the first field effect device is a P-channel metal oxide semiconductor field effect (PMOS) transistor.  
     
     
         15 . A method as recited in  claim 14 , wherein the second field effect device is an N-channel metal oxide semiconductor field effect (NMOS) transistor.  
     
     
         16 . A method as recited in  claim 15 , further comprising the operation of tracking the current in the first field effect device utilizing a current mirror.  
     
     
         17 . A method as recited in  claim 16 , wherein the current mirror tracks the current in the first field effect device at a predetermined ratio.  
     
     
         18 . A method as recited in  claim 11 , further comprising the operation of producing an essentially rail-to-rail output voltage, the essentially rail-to-rail output voltage being no more than one V GS  and two V Dsat  from either rail.  
     
     
         19 . An application specific integrated circuit (ASIC) having an output stage for a low voltage operational amplifier, the ASIC comprising: 
 a first field effect device having a first source, first drain, and first gate, the first source being coupled to a power supply V CC ;    a second field effect device complementary to the first field effect device, wherein the second field effect device includes a second source, second drain, and second gate, and wherein the second source is coupled to a power supply having a nominal voltage supply of V EE  and wherein the second drain is coupled to the first drain; and    an output sink network coupled to the second gate, wherein the output sink network drives the second field effect device such that a product of a first current in the first field effect device and a second current in the second field effect device is essentially equal to a predetermined constant during operation of the output stage.    
     
     
         20 . An ASIC as recited in  claim 19 , wherein the first field effect device is configured in a common source configuration.  
     
     
         21 . An ASIC as recited in  claim 19 , wherein the first field effect device is a P-channel metal oxide semiconductor field effect (PMOS) transistor.  
     
     
         22 . An ASIC as recited in  claim 21 , wherein the second field effect device is an N-channel metal oxide semiconductor field effect (NMOS) transistor.  
     
     
         23 . An ASIC as recited in  claim 22 , wherein the output sink network utilizes a current mirror to track the current in the first field effect device.  
     
     
         24 . An ASIC as recited in  claim 23 , wherein the current mirror tracks the current in the first field effect device at a predetermined ratio. A method as recited in  claim 13 , wherein the current mirror tracks the current in the first field effect device at a predetermined ratio.  
     
     
         25 . An ASIC as recited in  claim 24 , wherein the predetermined ratio is about 6:1.  
     
     
         26 . An ASIC as recited in  claim 19 , wherein a substantially rail-to-rail output voltage produced by the output stage is no more than one V GS  and two V Dsat  from either rail.  
     
     
         27 . An operational amplifier output stage suitable for low voltage operation and capable of providing a substantially rail-to-rail output voltage, the output stage comprising: 
 a push-pull output network, wherein the push-pull output network receives a first input signal and a second input signal, the first input signal being provided by an input signal V IN ; and    an output sink network, wherein the output sink network provides the second input signal to the push-pull output network.    
     
     
         28 . An operational amplifier output stage as recited in  claim 27 , wherein the push-pull output network includes a first field effect device and a second complimentary field effect device.  
     
     
         29 . An operational amplifier output stage as recited in  claim 28 , wherein the first field effect device is configured in a common source configuration.  
     
     
         30 . An operational amplifier output stage as recited in  claim 29 , wherein the output sink network utilizes a current mirror to track the current in the first field effect device.  
     
     
         31 . An operational amplifier output stage as recited in  claim 30 , wherein the current mirror tracks the current in the first field effect device at a predetermined ratio.  
     
     
         32 . An operational amplifier suitable for operating on low input voltages and capable of providing a substantially symmetrical rail-to-rail output voltage, the operational amplifier comprising: 
 an input stage; and    an output stage coupled to the input stage, wherein the output stage includes an output sink network.    
     
     
         33 . An operational amplifier as recited in  claim 32 , wherein the output stage further includes a push-pull output network, wherein the push-pull output network receives a first input signal and a second input signal, the first input signal being provided by an input signal V IN .  
     
     
         34 . An operational amplifier as recited in  claim 33 , wherein the output sink network provides the second input signal to the push-pull output network.