Methods to make DRAM fully compatible with SRAM

Abstract

This invention provides practical methods to make a DRAM fully compatible with existing SRAM products. This is accomplished by design and manufacture methods according to the invention, which includes a method to reduce standby power of reference voltage generators and a method to avoid the alpha particle problem using a novel error correction code (ECC) mechanism. The reference voltage generator of the present invention can adjust the values of output voltage and driving power separately following simple procedures. It has very strong driving power to maintain the reference voltage, which is necessary to support high- speed operation of memory devices of the present invention. In the mean time, its standby power can be reduced by orders of magnitudes using simple control mechanism, which is necessary to make our memory device compatible with the properties of existing SRAM products. There is no need to use feedback circuits or operation amplifiers, so the circuit is extremely stable and reliable. It is an ideal reference voltage generator to generate the bit line pre-charge voltage for a DRAM designed to emulate an SRAM device. The unique features of the ECC protection of the present invention avoid RC delay problems in prior art ECC circuits, which is necessary to support high speed operation of our products. The alpha particle problem is no longer an issue. All the supporting circuits can use repeated layouts, which is very important for memory design. The manufacture technology for embedded IC is simplified dramatically, which allow us to have high performance logic circuits. The memory devices of the present invention are therefore compatible in every detailed feature with existing SRAM products.

I claim:  
     
         1 . A reference voltage generator connected to a high voltage V CC  and a low voltage V SS  lower than V CC  for generating a reference voltage comprising: 
 a first variable-size p-channel transistor MPR having a source connected to said high voltage V CC , a gate connected to a voltage lower than said high voltage V CC ;    a first variable size n-channel transistor MN having a source and a gate connected to a drain of said transistor MPR;    a n-channel transistor MNO having a gate connected to said drain of said transistor MPR, a source connected to said voltage Vcc, and a drain connected to an output reference voltage Vout;    a second variable size p-channel transistor MP having a source connected to said drain of said transistor MN;    a second variable size n-channel transistor MNR having a drain connected to a gate and a drain of said transistor MP, a gate connected to a voltage higher than said low voltage V SS , and a source connected to said low voltage V SS ;    a p-channel transistor MPO having a gate connected to said drain of said transistor MP, a source connected to said low voltage V SS  and a drain connected to said output reference voltage; and    said MNO transistor is a matching transistor with said transistor MN and said transistor MPO is a matching transistor with said transistor MP wherein (Wmno/Wmn)=(Wmpo/Wmp)=Mc where Wmno is a width of said transistor MNO, Wmn is a variable width of said transistor MN, Wmpo is a width of said transistor MPO, Wmp is a variable width of said transistor MP, and Mc is a variable transistor matching ratio.    
     
     
         2 . The reference voltage generator of  claim 1  wherein: 
 said first variable-size p-channel MPR defining an adjustable effective resistance Rp and said first variable-size n-channel transistor MNR defining an adjustable effective resistance Rn; and  
 said output reference voltage Vout generated from said reference voltage generator constituting a voltage adjustable by adjusting a ratio of said effective resistance Rp to said effective resistance Rn.  
 
     
     
         3 . The reference voltage generator of  claim 2  wherein: 
 a connection between said n-channel transistor MNO and said p-channel transistor MPO defining a standby leakage current Istb therein, and said standby leakage current Istb is provided for adjustment by adjusting said variable transistor matching ratio Mc and a sum of said adjustable effective resistances defined by (Rp+Rn).  
 
     
     
         4 . The reference voltage generator of  claim 2  wherein: 
 said first variable-size n-channel transistor MN and said second variable-size p-channel transistor MP are provided with a transistor width adjustment means for receiving control signals for adjusting said variable transistor matching ratio Mc to adjust said standby leakage current in response to said control signal.  
 
     
     
         5 . The voltage reference generator of  claim 1  wherein: 
 said first variable-size p-channel transistor MPR further includes two p-channel transistors MPR 1  and MPR 2  connected in series and a switch SPR;  
 said switch SPR is connected to an activating voltage ZZ provided to control a serial connection of said second p-channel transistor MPR 2  between said first p-channel transistor MPR 1  and said n-channel transistor MN thus adjusting a size and effective resistance of said first variable-size p-channel transistor MPR;  
 said first variable size n-channel transistor MN further includes two n-channel transistors MN 1  and MN 2  connected in parallel and a switch SN;  
 said switch SN is connected to said activating voltage ZZ provided to control a parallel connection of said second n-channel transistor MN 2  to said first n-channel transistor MN 1  thus adjusting a size and said variable width Wmn of said variable-size n-channel transistor MN;  
 said second variable-size n-channel transistor MNR further includes two n-channel transistors MNR 1  and MNR 2  connected in series and a switch SNR;  
 said switch SNR is connected to an activating voltage ZZ provided to control a serial connection of said second p-channel transistor MNR 2  between said first n-channel transistor MNR 1  and said p-channel transistor MP thus adjusting a size and effective resistance of said second variable-size n-channel transistor MNR;  
 said second variable size p-channel transistor MP further includes two p-channel transistors MP 1  and MP 2  connected in parallel and a switch SP;  
 said switch SP is connected to said activating voltage ZZ provided to control a parallel connection of said second p-channel transistor MP 2  to said first p-channel transistor MP 1  thus adjusting a size and said variable width Wmp of said variable-size p-channel transistor MP.  
 
     
     
         6 . The voltage reference generator of  claim 5  wherein: 
 said first variable-size p-channel transistor MPR and said second variable-size n-channel transistor MNR are adjusted to define substantially a constant ratio of R P  to R N  to maintain said output reference voltage substantially unchanged.  
 
     
     
         7  A method for generating an output reference voltage comprising: 
 connecting a source of a first variable-size p-channel transistor MPR to a high voltage V CC  and a gate of said transistor MPR to a voltage lower than said high voltage V CC ;  
 connecting a gate and a source of a first variable-size n-channel transistor MN to a drain of said p-channel transistor MPR;  
 connecting a gate of a n-channel transistor MNO to said drain of transistor MPR, connecting a source of said n-channel transistor MNO to said a voltage higher than said low voltage V SS , and connecting a drain of said n-channel transistor MNO to said output reference voltage Vout;  
 connecting a source of a second variable size p-channel transistor MP to said drain of said variable-size n-channel transistor MN;  
 connecting a drain of a second variable-size n-channel transistor MNR to a gate and a drain of said p-channel transistor MP, and connecting a gate of said second variable-size n-channel transistor MNR to a voltage higher than a low V SS , and connecting a source of said transistor MNR to said low voltage V SS ;  
 connecting a gate of a p-channel transistor MPO to a drain of said transistor MP, connecting a source of said p-channel transistor MP to said low voltage V SS , and connecting a drain of said p-channel transistor MPO to said output reference voltage Vout;  
 matching said transistor MNO with said transistor MN and said transistor MPO to said transistor MP by providing (Wmno/Wmn)=(Wmpo/Wmp)=Mc where WMNO is a width of said transistor MNO, Wmn is a variable width of said transistor MN, Wmpo is a width of said transistor MPO, Wmp is a variable width of said transistor MP, and Mc is a variable transistor matching ratio.  
 
     
     
         8  The method of generating an output reference voltage of  claim 7  wherein: 
 configuring said first variable-size p-channel transistor MPR for defining an adjustable effective resistance Rp and said first variable-size n-channel transistor MNR for defining an adjustable effective resistance Rn; and  
 adjusting said output reference voltage Vout by adjusting a ratio of said effective resistance Rp to said effective resistance Rn.  
 
     
     
         9 . The method of generating an output reference voltage of  claim 7  wherein: 
 adjusting a standby leakage current Istb conducting from said n-channel transistor MNO to said p-channel transistor MPO by adjusting a said variable transistor matching ratio Mc and a sum of said adjustable effective resistance defined as (Rp+Rn).  
 
     
     
         10 . The method of generating an output reference voltage of  claim 7  wherein: 
 providing a control signal for controlling a width of said first variable-size n-channel transistor MN and said second variable-size p-channel transistor MP for adjusting said variable transistor matching ratio Mc to adjust a leakage current Istbr conducting from said transistor MN to said transistor MP.  
 
     
     
         11 . A memory circuit comprising a plurality of memory cells connected by a word-line, comprising: 
 a plurality of error correction code (ECC) logic circuits for generating a error correction code for each of said bits stored in said memory cells;    each of said memory cells being connected to one of said ECC logic circuits with every two of neighboring memory cells connected to two different ECC logic circuits.    
     
     
         12 . The memory circuit of  claim 11  wherein: 
 each of said plurality of memory cells being a dynamic random access memory (DRAM) cell.  
 
     
     
         13 . The memory circuit of  claim 11  wherein: 
 each of said error correction code (ECC) logic circuits being connected to N sets of memory bits for receiving input data bits D(i, j) and error correction bit C(i), for generating a set of correction bit F(i), where i=1, 2, 3, . . . N, and j=1, 2, 3, . . . , M, and N and M are positive integers,  
 each of said error correction code (ECC) logic circuits further includes a set of parity check blocks {P(i), i=1, 2, 3, . . . , N} wherein each of said parity check blocks P(i) being identical to each other and includes an external input means for receiving said input data bits D(i, j) and said error correction bit C(i);  
 each of said parity check blocks P(i) further includes a plurality of internal input means for receiving internal input bits from neighboring parity check block P(i−1) and P(i+1) and each of said parity check blocks P(i) further includes a plurality of internal output means for providing internal output bits to neighboring parity check block P(i−1) and P(i+1) wherein parity check block P(N) having two neighboring blocks of P(N−1) and P(1); and  
 each of said parity check blocks P(i) further includes an external output means for outputting said parity correction bit F(i) wherein a combination of said parity correction bits {F(i), i=1, 2, 3, . . . N} being provided as a N-bit error decoding input to a set of identical error decoding circuits {DC(i) i=1, 2, 3, . . . , N}, defined by a combination of said parity correction bits {F(i), i=1, 2, 3, . . . N} and said combination constituting a single-bit circular shifting relationship, and said error decoding circuits DC(i) generating a unique bit pattern for an error occurring to each of said data bits D(i, j).  
 
     
     
         14 . The memory circuit of  claim 13  wherein: 
 each of said parity checking blocks P(i), i=1, 2, 3, . . . , N being arranged physically next to two neighboring blocks and said parity check block P(N) being positioned next to said parity check block P(1) such that said internal input means and said internal output means are extended only to a neighboring parity check block.  
 
     
     
         15 . The memory circuit of  claim 14  further comprising: 
 an I/O device for zeroing out all of said error correction bits C(i)=0 for i=1, 2, 3, . . . , N, in a write cycle for generating said parity correction bits C(i)=F(i), i=1, 2, 3, . . . N, for writing into said memory cells.  
 
     
     
         16 . The memory circuit of  claim 14  further comprising: 
 an I/O device for transmitting said data D(i,j) and said error correction bits C(i)=0 to each of said ECC logic circuits for checking and correcting said data bits D(i, j) for reading said data bits D(i, j) from said memory.  
 
     
     
         17 . The memory circuit of  claim 13  wherein: 
 each of said logic circuits further includes a set of identical error decoding circuits DC(i) with i=1, 2, 3, . . . , N, and  
 each of said output means of said parity check blocks being connected, with a fixed identical combinations, as input lines, to said set of identical error decoding circuits DC(i), wherein said output means for each of said parity correction bits {F(i), i=1, 2, 3, . . . N} being rotationally shifted by a single bit line from a sequence of connection for that of D(i) when connected to a next error decoding circuits DC(i+1).  
 
     
     
         18 . A memory circuit comprising a plurality of memory cells connected by a word-line, wherein: 
 each of said memory cells having a cell refreshing rate requirement for periodically refreshing a bit stored therein with at least one of said memory cells having a highest refreshing rate;    said memory circuit further includes a plurality of error correction code (ECC) logic circuits connected to said memory cells for generating a error correction code for each of said bits stored in said memory cells to correct a bit error whereby said memory circuit is provided to operate with an overall refreshing rate lower than and independent of said highest refreshing rate.    
     
     
         19  A logic transistor supported on a substrate having an embedded memory transistor also supported on same substrate provided for connection to an error-code-correction (ECC) circuit and memory cells, wherein: 
 said logic transistor having a logic-transistor gate, a logic-transistor gate-oxide disposed under said logic-transistor gate, and a logic-transistor channel disposed under said logic-transistor gate oxide;  
 said memory transistor having a memory-transistor gate, a memory-transistor gate-oxide disposed under said memory-transistor gate, and a memory-transistor channel disposed under said logic-transistor gate oxide; and  
 said logic-transistor gate-oxide having substantially a same thickness as said memory-transistor gate-oxide, and said logic-transistor channel having substantially a same dopant concentration as said memory-transistor channel.  
 
     
     
         20 . The logic transistor of  claim 19  wherein: 
 said memory-transistor gate-oxide and said logic-transistor gate-oxide having a thickness less than or equal to one-hundred Angstroms.  
 
     
     
         21  A method for manufacturing a logic transistor on a substrate with an embedded memory transistor also on said substrate ready for connection to an error-code-correction (ECC) circuit, comprising: 
 forming an first-oxide layer;  
 performing an channel ion implant to form a logic-transistor channel and a gate-transistor channel having substantially same doping concentration followed by removing said first-oxide layer from said logic transistor and said memory transistor; and  
 forming a gate-oxide layer for said logic transistor and said memory transistor having substantially same thickness over said logic transistor channel and said memory-transistor channel.  
 
     
     
         22  The method for manufacturing said logic transistor of  claim 21  further comprising a step of: 
 forming a gate on top of said gate-oxide layer for said logic-transistor and said memory transistor having substantially same thickness.  
 
     
     
         23  The method for manufacturing said logic transistor of  claim 21  wherein: 
 said step of forming said gate-oxide layer for said logic transistor and said memory transistor is a step of forming said gate-oxide layer with a thickness less than or equal to one-hundred Angstroms.  
 
     
     
         24  The method for manufacturing said logic transistor of  claim 21  wherein: 
 said step of performing an channel ion implant to form a logic-transistor channel and a gate-transistor channel is a step of forming said logic-transistor channel and said gate-transistor channel having a channel length less than or equal to 0.5 micrometers.