US2002115229A1PendingUtilityA1

Semiconductor light-emitting elements

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Assignee: ROHM CO LTDPriority: Apr 15, 1999Filed: Apr 9, 2002Published: Aug 22, 2002
Est. expiryApr 15, 2019(expired)· nominal 20-yr term from priority
Inventors:Tsuyoshi TsutsuiKotaro Ogura
H10H 20/82
40
PatentIndex Score
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Claims

Abstract

Semiconductor light-emitting elements are produced by providing a wafer substrate of GaP, epitaxially growing on this substrate a semiconductor layered structure including an n-type layer and a p-type layer of GaP for providing a light-emitting layer, forming top electrodes on the semiconductor layered structure each over a portion of the area corresponding to one of the chips into which the substrate is to be later divided, forming a bottom electrode on the bottom surface of the substrate, dicing the wafer substrate into the individual chips, and thereafter carrying out a surface-roughening process on externally exposed portions of the semiconductor structure by means of hydrochloric acid. Each of the top electrodes is of a three-layer structure with a contact metal layer which may be of an alloy of Au and makes an ohmic contact with the GaP of the semiconductor layered structure, a Mo layer on the contact metal layer and an Au layer on the Mo layer.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A method of producing semiconductor light-emitting elements, said method comprising the steps of: 
 providing a wafer substrate comprising GaP, having a top surface and a bottom surface;    epitaxially growing on said top surface of said substrate a semiconductor layered structure including an n-type layer and a p-type layer comprising GaP, said n-type layer and said p-type layer forming a light-emitting layer,    forming top electrodes on said semiconductor layered structure each over a portion of an area corresponding to one of chips into which said substrate is to be later divided, each of said top electrodes being of a three-layer structure consisting of a contact metal layer which makes an ohmic contact with the GaP of said semiconductor layered structure, a Mo layer on said contact metal layer and an Au layer on said Mo layer;    forming a bottom electrode on said bottom surface of said substrate;    dicing said wafer substrate into said chips; and    thereafter carrying out a surface-roughening process on externally exposed portions of said semiconductor layered structure by means of hydrochloric acid.    
     
     
         2 . The method of  claim 1  wherein said surface-roughening process is carried out to obtain surface roughness of 0.1-3 μm in terms of height difference between protrusions and indentations on said externally exposed portions.  
     
     
         3 . The method of  claim 1  wherein said top electrodes are formed by vacuum vapor deposition.  
     
     
         4 . The method of  claim 1  wherein said Mo layer is formed to a thickness of 100-3000 Å.  
     
     
         5 . The method of  claim 1  wherein said contact metal layer comprises an alloy of Au, having a thickness of 500-3000 Å.  
     
     
         6 . The method of  claim 1  wherein said Au layer is formed to a thickness of 2000-12000 Å.  
     
     
         7 . The method of  claim 1  wherein said n-type layer and said p-type layer of said semiconductor layered structure are each formed to a thickness of 10- 100μm.    
     
     
         8 . The method of  claim 1  wherein said n-type layer and said p-type layer of said semiconductor layered structure are each made to have carrier concentration in the range of 5×10 17 −5×10 18  cm −3 .  
     
     
         9 . The method of  claim 1  wherein said surface-roughening process is carried out by means of a solution of hydrochloric acid with concentration at 10-35 weight %.  
     
     
         10 . A semiconductor element comprising: 
 a substrate comprising GaP, having a top surface and a bottom surface;    a semiconductor layered structure which is epitaxially grown on said top surface of said substrate and includes an n-type layer and a p-type layer comprising GaP, said n-type layer and said p-type layer forming a light-emitting layer; and    a top electrode on said semiconductor layered structure, said top electrode being of a three-layer structure consisting of a contact metal layer which makes an ohmic contact with the GaP of said semiconductor layered structure, a Mo layer on said contact metal layer and an Au layer on said Mo layer.    
     
     
         11 . The semiconductor element of  claim 10  further comprising a bottom electrode on said bottom surface of said substrate.  
     
     
         12 . The semiconductor element of  claim 10  wherein said layered structure has externally exposed surfaces with surface roughness of 0.1-3 μm in terms of height difference between protrusions and indentations.  
     
     
         13 . The semiconductor element of  claim 10  wherein said Mo layer has a thickness of 100-3000 Å.  
     
     
         14 . The semiconductor element of  claim 10  wherein said contact metal layer comprises an alloy of Au, having a thickness of 500-3000 Å.  
     
     
         15 . The semiconductor element of  claim 10  wherein said Au layer has a thickness of 2000-12000 Å.  
     
     
         16 . The semiconductor element of  claim 10  wherein said n-type layer and said p-type layer of said semiconductor layered structure each have a thickness of 10- 100 μm.    
     
     
         17 . The semiconductor element of  claim 10  wherein said n-type layer and said p-type layer of said semiconductor layered structure each have carrier concentration in the range of 5×10 17 −5×10 18  cm −3.

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