On-chip method and apparatus for transmission of multiple bits using quantized voltage levels

Abstract

A method and apparatus are disclosed for transmitting multiple bits among nodes on a chip using quantized voltage levels. Multiple level logic bus drivers and receivers communicate over a bus using a multiple-level logic protocol that transfers multiple bits on each signal wire of a bus in a given interval without increasing the bus width or power dissipation. In an exemplary embodiment, four logic levels are employed using CMOS transistor circuitry operating with low voltage (e.g., 1.2V or 1.3V) power supplies (V dd ) and P and N transistor threshold voltage levels of V tp and V tn on the order of 0.4−0.5V. Thus, the separation between the following four logic levels is approximately uniform: V dd ; V dd −V tp ; V ss +V tn ; and V ss . The approximately equal voltage gaps between each quantization level provide uniform noise margins for all levels. In addition, since the absolute magnitude of the coupling noise is much lower, it requires less active power to recover from an AC injected noise source. The number of physical wires on the bus is reduced by at least half for the same number of bits. The total transition power is reduced by more than fifty percent (50%) since some of the signal transitions are less than rail-to-rail. A bus noise minimization scheme and a quick recovery scheme are also disclosed to ensure the correct data transfer in the presence of injected noise. An initial over drive feature is disclosed for shorter transition times.

We claim:  
     
         1 . A method for communicating multiple bits among a plurality of nodes on a chip, said method comprising the steps of: 
 establishing a plurality of voltage levels on said chip; and    communicating over a bus using a multiple-level logic protocol    
     
     
         2 . The method of  claim 1 , wherein said plurality of voltage levels are substantially uniform.  
     
     
         3 . The method of  claim 1 , wherein said plurality of voltage levels are achieved using power supply voltages and threshold voltages of transistors on said chip.  
     
     
         4 . The method of  claim 3 , wherein said transistors are low voltage CMOS transistors.  
     
     
         5 . The method of  claim 4 , wherein said low voltage CMOS transistors utilize a power supply voltage of approximately 1.2V and have threshold voltages of approximately 0.4V.  
     
     
         6 . The method of  claim 4 , wherein said power supply voltages and threshold voltages provide a uniform level separation of approximately 0.3V.  
     
     
         7 . The method of  claim 3 , wherein said power supply voltages and threshold voltages establish four logic levels as follows: V dd ; V dd −V tp ; V ss +V tn ; and V ss , where V dd  is the power supply voltage, V ss  is 0V, V tp  is the P-transistor threshold voltage level and V tn  is the N-transistor threshold voltage level.  
     
     
         8 . A chip having a plurality of nodes, said chip comprising: 
 a common bus for communications between said nodes;    a first node having a multiple level logic bus driver that transmits multiple bits on a wire of said bus in a given time interval; and    a second node having a multiple level logic bus receiver that receives said multiple bits on said bus.    
     
     
         9 . The chip of  claim 8 , wherein said multiple levels are substantially uniform.  
     
     
         10 . The chip of  claim 8 , wherein said multiple levels are achieved in said multiple level logic bus driver using power supply voltages and threshold voltages of transistors on said chip.  
     
     
         11 . The chip of  claim 10 , wherein said transistors are low voltage CMOS transistors.  
     
     
         12 . The chip of  claim 11 , wherein said low voltage CMOS transistors utilize a power supply voltage of approximately 1.2V and have threshold voltages of approximately 0.4V.  
     
     
         13 . The chip of  claim 10 , wherein said power supply voltages and threshold voltages provide a uniform level separation of approximately 0.3V.  
     
     
         14 . The chip of  claim 10 , wherein said power supply voltages and threshold voltages establish four logic levels as follows: V dd ; V dd −V tp ; V ss +V tn ; and V ss , where V dd  is the power supply voltage, V ss  is 0V, V tp  is the P-transistor threshold voltage level and V tn  is the N-transistor threshold voltage level.  
     
     
         15 . A method for communicating multiple bits among a plurality of nodes on a chip, said method comprising the steps of: 
 establishing a plurality of voltage levels on said chip using power supply voltages and threshold voltages of transistors on said chip; and    communicating over a bus using a multiple-level logic protocol    
     
     
         16 . The method of  claim 15 , wherein said plurality of voltage levels are substantially uniform.  
     
     
         17 . The method of  claim 15 , wherein said transistors are low voltage CMOS transistors.  
     
     
         18 . The method of  claim 17 , wherein said low voltage CMOS transistors utilize a power supply voltage of approximately 1.2V and have threshold voltages of approximately 0.4V.  
     
     
         19 . The method of  claim 15 , wherein said power supply voltages and threshold voltages provide a uniform level separation of approximately 0.3V.  
     
     
         20 . The method of  claim 15 , wherein said power supply voltages and threshold voltages establish four logic levels as follows: V dd ; V dd −V tp ; V ss +V tn ; and V ss , where V dd  is the power supply voltage, V ss  is 0V, V tp  is the P-transistor threshold voltage level and V tn  is the N-transistor threshold voltage level.