US2002110954A1PendingUtilityA1

Semiconductor device and method of fabricating same

Assignee: MITSUBISHI ELECTRIC CORPPriority: Feb 26, 1998Filed: Apr 16, 2002Published: Aug 15, 2002
Est. expiryFeb 26, 2018(expired)· nominal 20-yr term from priority
H10W 74/147H10W 74/00H10W 72/01255H10W 72/01225H10W 72/952H10W 72/252H10W 72/242H10W 72/29H10W 72/20H10W 72/019H10W 72/012H10W 42/25H10D 30/67H10W 72/90
39
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film ( 107 ) is formed on a semiconductor substrate ( 101 ), and a MOS transistor having an SOI structure is formed on the buried oxide film ( 107 ). The MOS transistor comprises source and drain regions ( 120 a , 120 b ) formed in a semiconductor layer ( 120 ), and a gate electrode ( 110 ). An aluminum pad ( 103 ) connected to any one of the source and drain regions ( 120 a , 120 b ) through a connecting mechanism not shown, and a silicon nitride film ( 104 ) having an opening on the top of the aluminum pad ( 103 ) are formed on an interlayer insulation film ( 108 ). A layer of titanium ( 105 ) and a layer of nickel ( 106 ) are formed extending from the aluminum pad ( 103 ) to an end of the silicon nitride film ( 104 ). A solder bump ( 11 ) is disposed on the layer of nickel ( 106 ).

Claims

exact text as granted — not AI-modified
We claim:  
     
         1 . A semiconductor device comprising: 
 a semiconductor layer provided in an insulating layer and including a transistor having an SOI structure formed therein;    an electrode provided on said insulating layer; and    an electrically conductive bump provided on said electrode.    
     
     
         2 . The semiconductor device according to  claim 1 , 
 wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel.    
     
     
         3 . The semiconductor device according to  claim 1 , 
 wherein said transistor is a MOS transistor.    
     
     
         4 . The semiconductor device according to  claim 1 , 
 wherein said transistor includes a plurality of transistors field-shield isolated from each other and formed in said semiconductor layer.    
     
     
         5 . The semiconductor device according to  claim 4 , 
 wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel.    
     
     
         6 . A method of fabricating a semiconductor device, comprising the steps of: 
 (a) forming an electrode on a semiconductor substrate; and    (b) forming an electrically conductive bump on said electrode and    forming an insulating film for blocking an alpha ray and covering an upper surface of said semiconductor substrate except said electrode.    
     
     
         7 . The method according to  claim 6 , 
 wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel, and said insulating film is made of a polyimide.    
     
     
         8 . The method according to  claim 6 , 
 wherein said step (b) comprises the steps of 
 (b-1) forming said insulating film for blocking the alpha ray and covering the upper surface of said semiconductor substrate so that at least part of said electrode is exposed, and  
 (b-2) forming said electrically conductive bump on the exposed part of said electrode.  
   
     
     
         9 . The method according to  claim 8 , 
 wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel, and said insulating film is made of a polyimide.    
     
     
         10 . The method according to  claim 6 , 
 wherein said step (b) comprises the steps of 
 (b-1) forming said bump on said electrode, and  
 (b-2) dropping the material of said insulating film for blocking the alpha ray onto the upper surface of said semiconductor substrate except onto said electrode.  
   
     
     
         11 . The method according to  claim 10 , 
 wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel, and said insulating film is made of a polyimide.    
     
     
         12 . A semiconductor device comprising: 
 a semiconductor substrate;    an electrode disposed on said semiconductor substrate;    an electrically conductive bump provided on said electrode;    a film covering said semiconductor substrate except said bump and for blocking an alpha ray;    a first element disposed in said semiconductor substrate in an area that is visible from said bump without being obstructed by said film; and    a second element disposed in said semiconductor substrate in other than said area, said second element being less resistant to the alpha ray than said first element.    
     
     
         13 . The semiconductor device according to  claim 12 , 
 wherein said bump is a solder bump.    
     
     
         14 . The semiconductor device according to  claim 13 , 
 wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel, and said insulating film is made of a polyimide.    
     
     
         15 . The semiconductor device according to  claim 12 , 
 wherein said first element is a MOS transistor having a body at a fixed potential.    
     
     
         16 . The semiconductor device according to  claim 15 , 
 wherein said bump is a solder bump.    
     
     
         17 . The semiconductor device according to  claim 16 , 
 wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel, and said insulating film is made of a polyimide.    
     
     
         18 . A semiconductor device comprising: 
 a semiconductor substrate;    an electrode disposed on said semiconductor substrate;    an electrically conductive bump provided on said electrode;    a film covering said semiconductor substrate except said bump and for blocking an alpha ray;    an isolation oxide film disposed in said semiconductor substrate in an a re a that is visible from said bump without being obstructed by said film; and    an element disposed in said semiconductor substrate in other than said area.    
     
     
         19 . The semiconductor device according to  claim 18 , 
 wherein said bump is a solder bump.    
     
     
         20 . The semiconductor device according to  claim 19 , 
 wherein said electrode includes a multilayer structure comprised of a layer of titanium and a layer of nickel, and said insulating film is made of a polyimide.

Join the waitlist — get patent alerts

Track US2002110954A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.