Sense amplifier drive circuit

Abstract

A sense amplifier drive circuit has a sense amplifier amplifying data carried on a bit line and a bit line bar, a sense amplifier drive unit selectively applying an overdrive voltage or an internal power supply voltage to the sense amplifier, and a control signal generator combining a sense amplifier enable bar signal and a refresh enable signal, and generating control signals to control the sense amplifier drive unit. With the construction, an overdrive voltage is not supplied to the bit line and bit line bar during a refresh operation, and current consumption inevitably occurring during the refresh operation is much reduced.

What is claimed is:  
     
         1 . A circuit, comprising: 
 a sense amplifier that amplifies data carried on a bit line and a bit line bar;    a sense amplifier drive unit that selectively applies an overdrive voltage or an internal power supply voltage to the sense amplifier; and    a control signal generator that logically combines a sense amplifier enable bar signal and a refresh enable signal, and generates a plurality of control signals to control the sense amplifier drive unit.    
     
     
         2 . The circuit according to  claim 1 , wherein the control signal generator includes: 
 first and second inverters, each that invert the sense amplifier enable bar signal;    a delay circuit that delays an output signal from the second inverter for a predetermined time;    a third inverter that inverts output signal from the delay circuit;    a first NOR gate that performs a NOR operation to a combination of an output signal from the third inverter and the sense amplifier enable bar signal;    a fourth inverter that inverts an output from the second inverter;    a fifth inverter that inverts an output signal from the first NOR gate; and    a logic circuit that logically combines an output signal from the fourth inverter, an output signal from the fifth inverter and the refresh enable signal, to output the control signals.    
     
     
         3 . The circuit of  claim 2 , wherein the logic circuit includes: 
 a sixth inverter that inverts the output signal from the fifth inverter;    a seventh inverter that inverts the refresh enable signal;    a first control signal generator section that combines the output signal from the fourth inverter, an output signal from the sixth inverter and the refresh enable signal, and outputs a first one of the control signals;    a second control signal generator section that combines the output signal from the fourth inverter and the output signal from the sixth inverter, and outputs a second one of the control signals; and    a third control signal generator section that selectively outputs the output signal from the sixth inverter or the second control signal output from the second control signal generator section, and outputs a third one of the control signals.    
     
     
         4 . The circuit of  claim 3 , wherein the first control signal generator section includes: 
 a second NOR gate that performs a NOR operation on the output signal from the fourth inverter, the output signal from the sixth inverter, and the refresh enable signal; and    eighth and ninth inverters positioned in series that sequentially invert an output signal from the second NOR gate, and output the first control signal.    
     
     
         5 . The circuit of  claim 3 , wherein the second control signal generator section includes: 
 a tenth inverter that inverts the output signal from the sixth inverter;    a first NAND gate that performs a NAND operation on the output signal from the fourth inverter and an output signal from the tenth inverter; and    eleventh and twelfth inverters positioned in series, that sequentially invert an output signal from the first NAND gate, and output the second control signal.    
     
     
         6 . The circuit of  claim 5 , wherein the third control signal generator section includes: 
 thirteenth and fourteenth inverters positioned in series, that sequentially invert the output signal from the sixth inverter;    first transmission gate that selectively transmits an output signal from the first NAND gate under the control of the refresh enable signal and the output signal from the seventh inverter;    a second transmission gate that selectively transmits an output signal from the fourteenth inverter under the control of the refresh enable signal and the output signal from the seventh inverter; and    fifteenth and sixteenth inverters positioned in series that sequentially invert the signal selectively transmitted by the first and second transmission gates, and output the third control signal.    
     
     
         7 . A circuit, comprising: 
 a control signal generator that receives a sense amplifier signal and a refresh signal, that generates a first set of control signals based on the sense amplifier signal when the refresh signal is at a first level, and that generates a second set of control signals based on the sense amplifier signal when the refresh signal is at a second level;    a first drive circuit, coupled to the control signal generator, that enables the application of a first voltage according to the first and second set of control signals; and    a second drive circuit, coupled to the control signal generator, that enables the application of a second voltage according to the first set of control signals, and disables the application of the second voltage according to the second set of control signals.    
     
     
         8 . The circuit of  claim 7 , wherein the control signal generator includes a first section that selectively outputs one of the first set of control signals at an enabling level when the refresh signal is at the first level, and outputs one of the second set of control signals at a nonenabling level when the refresh signal is at the second level.  
     
     
         9 . The circuit of  claim 8 , wherein the control signal generator further includes a second section that outputs a second one of both the first and second set of control signals at a second enabling level when the sense amplifier signal is at a first level and outputs a second one of both the first and second set of control signals at a nonenabling level when the sense amplifier signal is at a second level.  
     
     
         10 . The circuit of  claim 9 , wherein the control signal further includes a third section that selectively outputs a third one of the first set of control signals at the enabling level when the refresh signal is at the first level, and that outputs a third one of the second set of control signals at a same level as the output from the second section when the refresh signal is at the second level.  
     
     
         11 . The circuit of  claim 7 , wherein the control signal generator includes a control signal generator section that outputs one of the second set of control signals at a nonenabling level during an entire period that the refresh signal is at the second level.  
     
     
         12 . The circuit of  claim 7 , wherein the first voltage is an internal power supply voltage, and the second voltage is an overdrive voltage.  
     
     
         13 . A method for amplifying data, comprising: 
 receiving a sense amplifier signal and a refresh signal;    generating a first set of control signals, based on the sense amplifier signal, when the refresh signal is at a first level;    generating a second set of control signals, based on the sense amplifier signal, when the refresh signal is at a second level;    enabling an application of a first voltage to a data signal according to the first and second set of control signals;    enabling an application of a second voltage to the data signal according to the first set of control signals; and    disabling an application of a second voltage to the data signal according to the second set of control signals.    
     
     
         14 . The method of  claim 13 , further comprising generating and outputting one of the first set of control signals at an enabling level when the refresh signal is at the first level and generating and outputting one of the second set of control signals at a non-enabling level when the refresh signal is at the second level.  
     
     
         15 . The method of  claim 14 , further comprising generating and outputting the second one of both the first and second sets of control signals at a second enabling level when the sense amplifier signal is at a first level, and generating and outputting the second one of both the first and second sets of control signals at a non-enabling level when the sense amplifier signal is at the second level.  
     
     
         16 . The method of  claim 15 , further comprising selectively generating and outputting a third one of the first set of control signals at the enabling level when the refresh signal is at the first level, and generating and outputting a third one of the second set of control signals at the second enabling level when the refresh signal is at the second level.  
     
     
         17 . The method of  claim 13 , further comprising outputting one of the second set of control signals at a non-enabling level during a period that the refresh signal is at the second level.  
     
     
         18 . A controller for a sense amplifier, comprising: 
 a first control circuit receiving a refresh enable signal and a sense enable signal to provide a first control signal for the sense amplifier;    second control circuit receiving a delayed sense enable signal to provide a second control signal for the sense amplifier; and    a third control circuit responsive to the refresh enable signal and a logically combined signal of the sense enable signal and the delayed sense enable signal to provide a third control signal for the sense amplifier, wherein said third control circuit includes first and second transmission gates having outputs commonly coupled to provide the third control signal and being responsive to at least one of the refresh enable signal and an inverted refresh enable signal.