Semiconductor device with improved metal interconnection and method for forming the metal interconnection

Abstract

A semiconductor device having a metal interconnection structure, and a method of forming a corresponding semiconductor device having a metal interconnection. The semiconductor device includes an interlevel dielectric (ILD) film deposited over a semiconductor substrate. The semiconductor substrate includes gate electrodes thereon separated from each other by an equal distance, and includes junction areas located between the gate electrodes, and is subjected to polishing. A portion of the ILD film aligned with a gate electrode is etched to a depth to form a trench. An anti-short insulating layer is deposited on the ILD film and in the trench. The anti-short insulating layer and the ILD film are etched to form a via hole so as to expose a junction area. The trench and the via hole are filled with metal, thereby resulting in a completed metal interconnection.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a substrate including a plurality of conductive areas therein;    an interlevel dielectric (ILD) film having a polished surface, the ILD film covering the substrate and having a via hole through which one of the plurality of the conductive areas is exposed and having a trench with a smaller depth than the via hole;    an anti-short insulating layer formed on sidewalls of the trench; and    a metal interconnection formed in the via hole and on the anti-short insulating layer in the trench.    
     
     
         2 . The semiconductor device of  claim 1 , wherein the anti-short insulating layer is also formed on a bottom of the trench.  
     
     
         3 . The semiconductor device of  claim 1 , wherein the anti-short insulating layer is also formed on a surface of the ILD film adjacent to the trench.  
     
     
         4 . The semiconductor device of  claim 1 , wherein the anti-short insulating layer is a same material as the ILD film.  
     
     
         5 . The semiconductor device of  claim 1 , wherein the anti-short insulating layer has a polishing selectivity of 15:1 or greater with respect to the metal interconnection.  
     
     
         6 . The semiconductor device of  claim 5 , wherein the anti-short insulating layer is a silicon nitride layer or a silicon oxynitride layer.  
     
     
         7 . The semiconductor device of  claim 1 , wherein the metal interconnection comprises: 
 an adhesive layer formed in the trench and in the via hole; and    a metal layer formed on the adhesive layer in the trench and in the via hole.    
     
     
         8 . A semiconductor device comprising: 
 a substrate including a plurality of conductive areas therein;    an interlevel dielectric (ILD) film having a polished surface, the ILD film covering the substrate and having a via hole through which one of the plurality of the conductive areas is exposed and having a trench with a smaller depth than the via hole;    an insulating spacer formed on sidewalls of the trench; and    a metal interconnection formed in the via hole and on the insulating spacer in the trench.    
     
     
         9 . The semiconductor device of  claim 8 , further comprising a polishing stop layer formed on the surface of the ILD film adjacent to the trench, on the insulating spacer in the trench, and on a bottom of the trench.  
     
     
         10 . The semiconductor device of  claim 9 , wherein the polishing stop layer and the insulating spacer are a same insulating material.  
     
     
         11 . The semiconductor device of  claim 10 , wherein the polishing stop layer and the insulating spacer are a same insulating material as the ILD film.  
     
     
         12 . The semiconductor device of  claim 10 , wherein the insulating spacer is an insulating material having a polishing selectivity of 15:1 or greater with respect to the metal interconnection.  
     
     
         13 . The semiconductor device of  claim 12 , wherein the insulating spacer is a silicon nitride layer or a silicon oxynitride layer.  
     
     
         14 . The semiconductor device of  claim 9 , wherein the metal interconnection comprises: 
 an adhesive layer formed in the trench and on the polishing stop layer in the via hole; and    a metal layer formed on the adhesive layer in the trench and in the via hole.    
     
     
         15 . A method of forming of a semiconductor device, comprising: 
 preparing a semiconductor substrate including a plurality of conductive areas therein;    forming an interlevel dielectric (ILD) film having a polished surface, on the semiconductor substrate;    etching a portion of the ILD film a depth to form a trench, wherein a selected one of the plurality of conductive areas is not located under the portion of the ILD film;    forming an anti-short insulating layer on the ILD film and in the trench;    etching the anti-short insulating layer and the ILD film to form a via hole through which the selected conductive area is exposed; and    forming a metal interconnection in the trench and the via hole.    
     
     
         16 . The method of  claim 15 , wherein the anti-short insulating layer is a same insulating material as the ILD film.  
     
     
         17 . The method of  claim 15 , wherein the anti-short insulating layer is an insulating material having a polishing selectivity of 15:1 or greater with respect to the metal interconnection.  
     
     
         18 . The method of  claim 17 , wherein the anti-short insulating layer is a silicon nitride layer or a silicon oxynitride layer.  
     
     
         19 . The method of  claim 15 , wherein said forming a metal interconnection comprises: 
 forming an adhesive layer in the via hole and on the anti-short insulating layer;    forming a metal layer on the adhesive so as to completely fill the trench and the via hole; and    polishing the metal layer and the adhesive layer until a surface of the anti-short insulating layer is exposed.    
     
     
         20 . A method of forming a semiconductor device, comprising: 
 preparing a semiconductor substrate including a plurality of conductive areas therein;    forming an interlevel dielectric (ILD) film having a polished surface, on the semiconductor substrate;    etching a portion of the ILD film a depth to form a trench, wherein a selected one of the plurality of conductive areas is not located under the portion of the ILD film;    forming an anti-short insulating layer on the ILD film and in the trench;    etching the anti-short insulating layer to expose the ILD film and so that the anti-short insulating layer remains as a spacer only on sidewalls of the trench;    etching the ILD film to form a via hole through which the selected conductive area is exposed; and    forming a metal interconnection in the trench and the via hole.    
     
     
         21 . The method of  claim 20 , wherein said forming a metal interconnection comprises: 
 forming an adhesive layer in the via hole, on the ILD film and on the sidewalls of the trench;    forming a metal layer on the adhesive layer so as to completely fill the trench and the via hole; and    polishing the metal layer and the adhesive layer until a surface of the ILD film is exposed.    
     
     
         22 . The method of  claim 21 , wherein after said etching to form the spacer and before said etching to form the via hole, further comprising forming a polishing stop layer on the ILD film and the spacer.  
     
     
         23 . The method of  claim 22 , wherein the polishing stop layer is a same insulating material as the anti-short insulating layer.  
     
     
         24 . The method of  claim 23 , wherein the anti-short insulating layer and the polishing stop layer are a same insulating material as the ILD film.  
     
     
         25 . The method of  claim 23 , wherein the anti-short insulating layer and the polishing stop layer are an insulating material having a polishing selectivity of 15:1 or greater with respect to the metal interconnection.  
     
     
         26 . The method of  claim 25 , wherein the anti-short insulating layer and the polishing stop layer are a silicon nitride layer or a silicon oxynitride layer.