MFMOS/MFMS non-volatile memory transistors and method of making same

Abstract

A method of fabricating a non-volatile ferroelectric memory transistor includes forming a bottom electrode, depositing a ferroelectric layer over an active region beyond the margins of the bottom electrode; depositing a top electrode on the ferroelectric layer, and metallizing the structure to form a source electrode, a gate electrode and a drain electrode. A non-volatile ferroelectric memory transistor includes a bottom electrode formed above a gate region, wherein the bottom electrode has a predetermined area within a peripheral boundary; a ferroelectric layer extending over and beyond the bottom electrode peripheral boundary; and a top electrode formed on said ferroelectric layer.

We claim:  
     
         1 . A method of fabricating a non-volatile ferroelectric memory transistor, comprising. 
 preparing a silicon substrate, including forming an active region on the substrate,    implanting ions to form a source region and a drain region in the active regions;    forming a bottom electrode;    depositing a ferroelectric layer over the active region;    depositing a top electrode;    depositing an insulating oxide layer over the active region; and    metallizing the structure to form a source electrode, a gate electrode and a drain electrode.    
     
     
         2 . The method of  claim 1  wherein said preparing includes forming a gate oxide layer in a gate region.  
     
     
         3 . The method of  claim 1  wherein said preparing includes forming a surface channel in a gate region  
     
     
         4 . The method of  claim 3  wherein said forming a surface channel region includes forming an n-region by implantation of Arsenic ions, at a dose of about 1·10 11  cm −2  to 5·10 12  cm −2 , and at an energy level of 15 keV to 30 keV.  
     
     
         5 . The method of  claim 1  wherein said forming a bottom electrode includes chemical vapor deposition of a layer of Iridium, deposited to a thickness of between about 100 nm and 200 nm, and which further includes etching the Iridium layer to form a bottom electrode of a predetermined area.  
     
     
         6 . The method of  claim 5  which further includes chemical vapor deposition of oxide to a thickness of between about 200 nm and 400 nm, and thinning the oxide layer by chemical mechanical polishing to the upper surface of bottom electrode, thereby exposing the upper surface of the bottom electrode.  
     
     
         7 . The method of  claim 1  wherein said implanting ions includes implanting Arsenic ions at a dose of about 1·10 15  cm −2  to 3·10 15  cm −2 , and at an energy level of 20 keV to 40 keV.  
     
     
         8 . The method of  claim 1  wherein said depositing a ferroelectric layer includes depositing a ferroelectric material by chemical vapor deposition to a thickness of between about 100 nm and 400 nm.  
     
     
         9 . The method of  claim 8  wherein said depositing includes depositing an ferroelectric material taken from the group of ferroelectric materials consisting of Pb(Zr, Ti)O 3  (PZT), SrBi 2 Ta 2 O 9  (SBT), Pb 5 Ge 3 O 11 , BaTiO 3 , and LiNbO 3    
     
     
         10 . The method of  claim 1  wherein said depositing a top electrode includes depositing a layer of Platinum, by a deposition process taken from the group of processes consisting of chemical vapor deposition and sputtering to a thickness of between about 100 nm and 300 nm, masking the desired area of the top electrode, and etching the unmasked material  
     
     
         11 . The method of  claim 10  wherein said depositing a top electrode includes forming a top electrode having an area greater than the area of the bottom electrode.  
     
     
         12 . The method of  claim 10  wherein said depositing a top electrode includes forming a top electrode having an area which overlaps the source region and the drain region.  
     
     
         13 . The method of  claim 1  which further includes forming a barrier insulation layer which extends over the ferroelectric layer and the top electrode  
     
     
         14 . The method of  claim 13  wherein said forming a barrier insulation layer includes depositing a layer of TiO 2  to a thickness of between about 10 nm and 30 nm  
     
     
         15 . A non-volatile ferroelectric memory transistor comprising: 
 a silicon substrate having an active region formed thereon;    a source region and a drain region formed about a gate region in said active region;    a bottom electrode formed above said gate region, wherein said bottom electrode has a predetermined area within a peripheral boundary;    a ferroelectric layer extending over and beyond the bottom electrode peripheral boundary,    a top electrode formed on said ferroelectric layer;    an insulating oxide layer; and    a source electrode, a gate electrode and a drain electrode    
     
     
         16 . The non-volatile ferroelectric memory transistor of  claim 15  which further includes a barrier insulation layer extending over said ferroelectric layer and said top electrode  
     
     
         17 . The non-volatile ferroelectric memory transistor of  claim 16  wherein said barrier insulation layer includes a layer of TiO 2  deposited to a thickness of between about 10 nm and 30 nm.  
     
     
         18 . The non-volatile ferroelectric memory transistor of  claim 15  wherein said top electrode has a surface area greater than said bottom electrode predetermined area.  
     
     
         19 . The non-volatile ferroelectric memory transistor of  claim 15  wherein said top electrode extends at least partially over said source region and said drain region.  
     
     
         20 . The non-volatile ferroelectric memory transistor of  claim 15  which further includes a gate oxide layer formed on said silicon substrate  
     
     
         21 . The non-volatile ferroelectric memory transistor of  claim 15  which further includes a surface channel layer formed on said silicon substrate  
     
     
         22 . The non-volatile ferroelectric memory transistor of  claim 15  wherein said bottom electrode is formed of Iridium to a thickness of between about 100 nm and 200 nm.  
     
     
         23 . The non-volatile ferroelectric memory transistor of  claim 15  wherein said ferroelectric layer is formed of a ferroelectric material taken from the group of ferroelectric materials consisting of Pb(Zr, Ti) 0   3  (PZT), SrBi 2 Ta 2 O 9  (SBT), Pb 5 Ge 3 O 11 , BaTiO 3 , and LiNbO 3 , and which is deposited to a thickness of between about 100 nm and 400 nm.  
     
     
         24 . The non-volatile ferroelectric memory transistor of  claim 15  wherein said top electrode is formed of Platinum to a thickness of between about 100 nm and 300 nm