Image acquisition system

Abstract

An image acquisition system for machine vision systems decouples image acquisition from the transmission of the image to a host processor by using a programmable imager controller to selectively disable and enable the transmission of data to the host and by using a system of buffers to temporarily store image data pending allocation of memory. This enables the image acquisition system to acquire images asynchronously and to change the exposure parameters on a frame-by-frame basis without the latency associated with the allocation of memory for storage of the acquired image. The system architecture of the invention further permits interruption and resumption of image acquisition with minimal likelihood of missing data. Data throughput is further enhanced by transmitting to the host only that data corresponding to the region of interest within the image and discarding the data from outside of the region of interest at the camera stage.

Having described the invention, what is claimed as new and desired to be secured by Letters patent is:  
     
         1 . A system for transmitting an image to a machine vision system having a host processor that allocates memory for storage of said image, said system comprising: 
 image acquisition means for acquiring at least a portion of said image in response to a trigger signal,    memory means for storing data representative of said image,    image transfer means for transferring said image from said image acquisition means to said memory means, said image transfer means including buffer memory means for temporarily storing said at least a portion of said image pending allocation of memory space from said memory means by the host processor,    wherein said image acquisition means can operate substantially independently of the allocation of memory by the host processor.    
     
     
         2 . A system according to  claim 1 , wherein said buffer memory means comprises a data FIFO register, said data FIFO being coupled to receive data representative of said image from said image acquisition means and to release data representative of said image to the host processor in response to a release signal.  
     
     
         3 . A system according to  claim 1 , wherein said buffer memory means comprises a plurality of registers, said plurality of registers being coupled to receive data representative of said image from said image acquisition means in response to said trigger signal and to release data representative of said image to the host processor in response to a release signal.  
     
     
         4 . A system according to  claim 1 , wherein said image acquisition means comprises 
 photo-sensitive means for acquiring said image in response to said trigger signal containing selected image acquisition parameters, and    programmable control means in circuit with said photo-sensitive means for generating said trigger signal and for programmably altering during acquisition of said image said selected image acquisition parameters.    
     
     
         5 . A system according to  claim 4 , wherein said photo-sensitive means includes a CCD array and said programmable control means includes a programmable imager controller.  
     
     
         6 . A system according to  claim 4 , wherein said programmable control means comprises: 
 a controller adapted to be programmed with said selected image acquisition parameters and for generating said trigger signal in response to a loading signal, and    parameter loading means coupled to said controller for generating said loading signal and for receiving said image acquisition parameters.    
     
     
         7 . A system according to  claim 4 , wherein said programmable control means includes a programmable imager controller circuit; said controller circuit being adapted to be programmed with said image acquisition parameters.  
     
     
         8 . A system according to  claim 7 , wherein said programmable imager controller circuit includes means for receiving said image acquisition parameters in less than or equal to about 2 μs.  
     
     
         9 . A system according to  claim 7 , wherein said programmable imager controller circuit includes means for reprogramming said circuit on the fly, in essentially real time.  
     
     
         10 . A system according to  claim 7 , wherein said programmable imager controller circuit operates at a driving frequency, said programmable imager controller circuit comprising means for automatically changing said driving frequency during acquisition of said image.  
     
     
         11 . A system according to  claim 6 , further comprising 
 actuation means for generating an output actuation signal in response to an input command signal, said parameter loading means generating said loading signal in response to said actuation signal, and    parameter memory means, in communication with said parameter loading means, for receiving said image acquisition parameters from the host processor.    
     
     
         12 . A system according to  claim 4 , wherein said image acquisition means further includes 
 actuation means for generating an output actuation signal in response to a command signal,    parameter memory means in communication with said programmable memory means for receiving said image acquisition parameters from the host processor, and    a camera loader circuit adapted to receive said selected image acquisition parameters from said parameter memory means and said output actuation signal, for programming said programmable control means with said image acquisition parameters.    
     
     
         13 . A system according to  claim 4 , wherein said buffer memory means comprises one or more vertical registers coupled to said photo-sensitive means for storing optical energy representative of said acquired image, and one or more horizontal registers positioned to receive at least a portion of said optical energy stored in said vertical register.  
     
     
         14 . A system according to  claim 13 , wherein said photo-sensitive means is adapted to acquire a region of interest corresponding to at least a portion of said image, and wherein said means for transferring tranfers a portion of said optical energy corresponding to a portion of said region of interest from said vertical register into said horizontal register, further comprising 
 disabling means for disabling transfer of said optical energy from said horizontal register during said transfer of optical energy from said vertical register into said horizontal register,    whereby said optical energy corresponding to a portion of said region of interest is rapidly transferred from said vertical register to said horizontal register without actively removing said stored energy from said horizontal register.    
     
     
         15 . A system according to  claim 14 , wherein said photo-sensitive means is adapted to acquire a region of interest corresponding to at least a portion of said image, and wherein said means for transferring tranfers a portion of said energy stored in said vertical register corresponding to a portion of said region of interest into said horizontal register, further comprising 
 enabling means for enabling transfer of said optical energy stored in said horizontal register therefrom, and 
 disabling means for disabling transfer of optical energy from said vertical register into said horizontal register during said transfer of optical energy out of said horizontal register.  
   
     
     
         16 . A system according to  claim 2 , further comprising direct memory address data transfer means for transferring said image data accumulated in said data FIFO register directly memory allocated in the host computing system, whereby said data tranfer substantially reduces the number of times said system interrupts the host processor.  
     
     
         17 . A system according to  claim 2 , further comprising pre-processing means separate from the host processor for receiving said image data and for at least partially processing said data without substantially interrupting the host processor.  
     
     
         18 . A system according to  claim 2 , further comprising interrupt means coupled to said data FIFO register and to said image acquisition means for interrupting said acquisition of said image when said data FIFO register is at least substantially full, thereby permitting reliable transfer of data corresponding to said image.  
     
     
         19 . A system according to  claim 18 , wherein said image is composed of a plurality of lines, and wherein said interrupt means is capable of interrupting said acquisition of said image between said lines corresponding to said image.  
     
     
         20 . A system according to  claim 2 , further comprising feedback means coupled between said image acquisition means and said data FIFO register for monitoring said status of said register and for transferring an interrupt signal to said image acquisition means to interrupt said acquisition of said image, said feedback means including interrupt means coupled to said data FIFO register for generating said interrupt signal when said data FIFO register is at least substantially full, whereby said interrupt means immediately and temporarily interrupts said acquisition of said image.  
     
     
         21 . A system according to  claim 1 , wherein said image acquisition means acquires said image in parallel with and substantially independently of allocation of memory by the host processor.  
     
     
         22 . A system according to  claim 1 , wherein said image acquired by said image acquisition means includes a plurality of pixels, further comprising pixel correction means in circuit with said image acquisition means for correcting said pixels prior to transfer to said memory means.  
     
     
         23 . A system according to  claim 22 , wherein said pixel correction means comprises 
 second memory means for storing a plurality of pre-determined pixel correction values corresponding to each pixel of said image, and    multiplier means for multiplying each pixel of said image by said corresponding pixel correction value, thereby forming a corrected pixel.    
     
     
         24 . A system according to  claim 22 , wherein said pixel correction means is separate from the host processor and performs said pixel correction in real time.  
     
     
         25 . A system according to  claim 4 , wherein said image has a region of interest corresponding to a portion of said image, said region of interest having a selected number of pixels, further comprising 
 pixel evaluation memory means coupled to image acquisition means for storing a value corresponding to said selected number of pixels,and    pre-determined pixel storage means coupled to said image acquisition means for storing a value corresponding to a predetermined number of pixels.    
     
     
         26 . A system according to  claim 25 , further comprising 
 comparing means for comparing said value stored in said pixel evaluation means with said value stored in said pre-determined pixel storage means, and    means for generating a match signal when said values are equal, said programmable control means including means for receiving said match signal and for altering said image acquisition parameters.    
     
     
         27 . A machine vision system for acquiring an image, said system comprising: 
 image acquisition means for acquiring said image, said image acquisition means including means for altering image acquisition parameters prior to acquisition of said image;    memory means for storing said image;    image transfer means for transferring said image from said programmable image acquisition means to said memory means, said image transfer means including 
 means for interrupting transfer of said image at an interruption point, and  
 means for resuming transfer of said image from said interruption point.  
   whereby resuming said acquisition of said image at said interruption point substantially prevents loss of data corresponding to said image.    
     
     
         28 . A system according to  claim 27 , wherein said image acquisition means includes means for defining at least one region of interest, said at least one region of interest being a subset of said image, and means for acquiring said at least one region of interest.  
     
     
         29 . A system according to  claim 28 , wherein said at least one region of interest is a rectangular region of interest having a first comer and a second comer diagonally opposite said first corner, said at least one region of interest being defined by the coordinates of said first comer and the coordinates of said second comer.  
     
     
         30 . A system according to  claim 27 , wherein said image acquisition means comprises means for programmably controlling the amount of optical energy corresponding to said image collected by a camera.  
     
     
         31 . A system according to  claim 27 , wherein said image acquisition means includes trigger means for initiating acquisition of said image in response to a trigger signal.  
     
     
         32 . A system according to  claim 27 , wherein said image acquisition means includes a camera.  
     
     
         33 . A system according to  claim 27 , wherein said image acquisition means includes image correction means for multiplying a subset of said image by a correction value corresponding to said subset of said image.  
     
     
         34 . A system according to  claim 33 , wherein said image correction means comprises 
 image input means for accepting data representative of said image,    storage means for storing said correction factor corresponding to said subset of said image, said storage means having input means responsive to an external signal,    multiplier means coupled to said storage means and coupled to said image input means for multiplying said correction value with said corresponding subset of said image, and    data counter means coupled to said storage table means for determining correspondence between said subset of said image and said correction value.    
     
     
         35 . A system according to  claim 27 , wherein said image acquisition means includes means for encoding an acquisition time into said image.  
     
     
         36 . A system according to  claim 27 , wherein said means for encoding an acquisition time into said image comprises kernel level software in communication with a host processor, said kernel level software being responsive to a camera trigger signal.  
     
     
         37 . A system according to  claim 27 , wherein said image transfer means includes a data FIFO memory for storing data and for releasing data asynchronously.  
     
     
         38 . A system according to  claim 27 , wherein said image transfer means includes programmable imager data transfer means for selectively controlling the rate at which data travels from said image acquisition means to said memory means.  
     
     
         39 . A system according to  claim 38 , wherein said programmable imager transfer means comprises 
 first data storage means for storing said image acquired by said image acquisition means,    second data storage means coupled to said first data storage means,    first shift means for shifting a subset of said image stored in said first data storage means to said second data storage means thereby storing said subset of said image in said second data storage means,    second shift means for shifting said subset of said image stored in said second data storage means to said memory means, and    disable means for disabling said second shift means during operation of said first shift means and to disable said first shift means during operation of said second shift means.    
     
     
         40 . A system according to  claim 27 , wherein said image transfer means comprises 
 first data storage means for storing said image acquired by said image acquisition means,    second data storage means coupled to said first data storage means,    first shift means for shifting a subset of said image stored in said first data storage means to said second data storage means thereby storing said subset of said image in said second data storage means,    second shift means for shifting said subset of said image stored in said second data storage means to said memory means, and    disable means for disabling said second shift means during operation of said first shift means and to disable said first shift means during operation of said second shift means, said disable means including 
 means for operating said second shift means when said image stored in said second data storage means is inside said region of interest, and  
 second disabling means for disabling said second shift means and operating said first shift means when said image stored in said second data storage means is outside said region of interest.  
   
     
     
         41 . A system according to  claim 27 , wherein said image acquisition means comprises a CCD array and a programmable imager CCD controller coupled to said CCD array.  
     
     
         42 . A system according to  claim 27 , wherein said image acquisition means comprises 
 photo-sensitive means for acquiring said image in response to an acquisition signal containing selected image acquisition parameters, and    programmable control means in circuit with said photo-sensitive means for generating said acquisition signal and for programmably altering during acquisition of said image said selected image acquisition parameters.    
     
     
         43 . A system according to  claim 42 , wherein said programmable control means comprises: 
 a controller adapted to be programmed with said selected image acquisition parameters and for generating said acquisition signal in response to a loading signal, and    parameter loading means coupled to said controller for generating said loading signal and for receiving said image acquisition parameters.    
     
     
         44 . A system according to  claim 42 , wherein said programmable control means includes a programmable imager controller circuit, said controller circuit being adapted to be programmed with said image acquisition parameters.  
     
     
         45 . A system according to  claim 44 , wherein said programmable imager controller circuit includes means for receiving said image acquisition parameters in less than or equal to about 2 μs.  
     
     
         46 . A system according to  claim 42 , wherein said programmable imager controller circuit includes means for reprogramming said controller circuit on the fly, in essentially real time.  
     
     
         47 . A system according to  claim 44 , wherein said programmable imager controller circuit operates at a driving frequency, said programmable imager controller circuit comprising means for automatically changing said driving frequency during acquisition of said image.  
     
     
         48 . A system according to  claim 43 , further comprising 
 triggering means for generating a trigger signal in response to an input command signal, said parameter loading means generating said loading signal in response to said trigger signal, and    parameter memory means coupled to said paramter loading means for receiving and storing said image acquisition parameters from the host processor.    
     
     
         49 . A system according to  claim 27 , wherein said image acquisition means further includes 
 triggering means for generating an output trigger signal in response to a command signal,    parameter memory means adapted for receiving said image acquisition parameters from the host processor, and    a camera loader circuit adapted to receive said selected image acquisition parameters from said parameter memory means and said output trigger signal, for programming said programmable control means with said image acquisition parameters.    
     
     
         50 . A system according to  claim 27 , wherein said memory means comprises a data FIFO register, wherein said means for transferring transfers said image into said register.  
     
     
         51 . A system according to  claim 50 , further comprising data transfer means for transferring said image data accumulated in said data FIFO register to the host computing system.  
     
     
         52 . A system according to  claim 51 , wherein said transfer of data from said data FIFO register is a direct memory address transfer, thereby substantially reducing the number of times the system interrupts the host processor.  
     
     
         53 . A system according to  claim 27 , further comprising pre-processing means separate from the host processor for receiving said image data and for at least partially processing said data without interrupting said host processor.  
     
     
         54 . A system according to  claim 14 , wherein said means for interrupting is coupled to said data FIFO register and to said image acquisition means for interrupting said acquisition of said image when said data FIFO register is full, thereby permitting reliable transfer of data corresponding to said image.  
     
     
         55 . A system according to  claim 51 , wherein said data transfer means transfers data from said data FIFO register substantially independently of the memory manager of the host computing system.  
     
     
         56 . A system according to  claim 27 , wherein said means for transferring is adapted for immediately and temporarily interrupting said acquisition of said image.  
     
     
         57 . A system according to  claim 42 , wherein the host processor allocates memory for storage of said image, and wherein said programmable control means generates said acquisition signal substantially independently of allocation of the memory by the host processor.  
     
     
         58 . A system according to  claim 42 , wherein the host processor allocates memory for storage of said image, and wherein said programmable control means generates said acquisition signal in parallel with and substantially independently of allocation of the memory by the host processor.  
     
     
         59 . A system for transmitting an image to a machine vision system having a host processor that allocates memory for storage of said image, said system comprising: 
 image acquisition means for acquiring at least a portion of said image in response to a trigger signal;    image transfer means for transferring said image from said image acquisition means to memory allocated by the host processor, said image transfer means including 
 transfer interruption means for interrupting transfer of said image to memory at an interruption point,  
 buffer means coupled to receive data representative of an image from said image acquisition means for storing said data during the operation of said transfer interruption means, and  
 transfer resumption means to resume transfer of said image to memory from said interruption point.  
   
     
     
         60 . An image acquisition system for connection to a machine vision system for acquiring an image of an object, said systen having a host processor and comprising: 
 image acquisition means for acquiring said image of the object, said image acquisition means including 
 photo-sensitive means for acquiring said image in response to an acquisition signal containing selected image acquisition parameters, and  
 programmable control means in circuit with said photo-sensitive means for generating said acquisition signal and for programmably altering during acquisition of said image said selected image acquisition parameters,  
   memory means for storing at least a portion of said image, and    transfer means for transferring said image from said image acquisition means to said memory means.    
     
     
         61 . The image acquisition system of  claim 60 , wherein said photo-sensitive means includes a CCD array and said programmable control means includes a programmable imager CCD controller.  
     
     
         62 . The image acquisition system of  claim 60 , wherein said programmable control means comprises: 
 a controller adapted to be programmed with said selected image acquisition parameters and for generating said acquisition signal in response to a loading signal, and    parameter loading means coupled to said controller for generating said actuation signal and for receiving said image acquisition parameters.    
     
     
         63 . The image acquisition system of  claim 60 , wherein said programmable control means includes a programmable imager controller circuit, said controller circuit being adapted to be programmed with said image acquisition parameters.  
     
     
         64 . The image acquisition system of  claim 63 , wherein said programmable imager controller circuit includes means for receiving said image acquisition parameters in less than or equal to about 2 μs.  
     
     
         65 . The image acquisition system of  claim 63 , wherein said programmable imager controller circuit includes means for reprogramming said circuit on the fly, in essentially real time.  
     
     
         66 . The image acquisition system of  claim 63 , wherein said programmable imager controller circuit operates at a driving frequency, said programmable imager controller circuit comprising means for automatically changing said driving frequency during acquisition of said image.  
     
     
         67 . The image acquisition system of  claim 62 , further comprising 
 triggering means for generating a trigger signal in response to an input command signal, said parameter loading means generating said loading signal in response to said trigger signal, and    parameter memory means for receiving and storing said image acquisition parameters from the host processor.    
     
     
         68 . The image acquisition system of  claim 60 , wherein said image acquisition means further includes 
 triggering means for generating an output trigger signal in response to a command signal,    parameter memory means adapted for receiving said image acquisition parameters from the host processor, and    a camera loader circuit adapted to receive said selected image acquisition parameters from said parameter memory means and said output trigger signal, for programming said programmable control means with said image acquisition parameters.    
     
     
         69 . The image acquisition system of  claim 60 , wherein said memory means comprises one or more vertical registers coupled to said photo-sensitive means for storing optical energy representative of said acquired image, and one or more horizontal registers positioned to receive at least a portion of said optical energy stored in said vertical register.  
     
     
         70 . The image acquisition system of  claim 69 , wherein said photo-sensitive means is adapted to acquire a region of interest corresponding to at least a portion of said image, further comprising 
 second means for transferring a portion of said optical energy corresponding to a portion of said region of interest from said vertical register to said horizontal register, and    disabling means for disabling transfer of optical energy from said horizontal energy during said transfer of optical energy from said vertical register into said horizontal register,    whereby said optical energy corresponding to a portion of said region of interest is rapidly transferred from said vertical register to said horizontal register without actively removing said transferred energy from said horizontal register.    
     
     
         71 . The image acquisition system of  claim 70 , wherein said photo-sensitive means is adapted to acquire a region of interest corresponding to at least a portion of said image, further comprising 
 second means for transferring a portion of said energy stored in said vertical register corresponding to a portion of said region of interest to said horizontal register,    enabling means for enabling transfer of optical energy stored in said horizontal register therefrom, and    disabling means for disabling transfer of optical energy from said vertical register into said horizontal register during said transfer of optical energy out of said horizontal register.    
     
     
         72 . The image acquisition system of  claim 60 , wherein said memory means comprises a data FIFO register, wherein said transfer means transfers said image into said register.  
     
     
         73 . The image acquisition system of  claim 72 , further comprising second transfer means for transferring said image data accumulated in said data FIFO register to the host computing system.  
     
     
         74 . The image acquisition system of  claim 72 , further comprising memory address transfer means for transferring said data stored in said data FIFO register directly to an address in the host computing system, thereby substantially reducing the number of times the system interrupts the host processor.  
     
     
         75 . The image acquisition system of  claim 72 , further comprising pre-processing means separate from the host processor for receiving said image data and for at least partially processing said data without interrupting said host processor.  
     
     
         76 . The image acquisition system of  claim 72 , further comprising interrupt means coupled to said data FIFO register and to said image acquisition means for interrupting said acquisition of said image when said data FIFO register is full, thereby permitting reliable transfer of data corresponding to said image.  
     
     
         77 . The image acquisition system of  claim 76 , wherein said interrupt means is capable of interrupting said acquisition of said image between lines corresponding to said image.  
     
     
         78 . The image acquisition system of  claim 15 , wherein said second transfer means transfers data from said data FIFO register substantially independently of the memory manager of the host computing system.  
     
     
         79 . The image acquisition system of  claim 76 , wherein said interrupt means is adapted for immediately and temporarily interrupting said acquisition of said image.  
     
     
         80 . The image acquisition system of  claim 60 , wherein the host processor allocates memory for storage of said image, and wherein said programmable control means generates said acquisition signal substantially independently of allocation of the memory by the host processor.  
     
     
         81 . The image acquisition system of  claim 60 , wherein the host processor allocates memory for storage of said image, and wherein said programmable control means generates said acquisition signal in parallel with and substantially independently of allocation of the memory by the host processor.  
     
     
         82 . The image acquisition system of  claim 60 , wherein said image acquired by said image acquisition means includes a plurality of pixels, further comprising pixel correction means in circuit with said image acquisition means for correcting said pixels prior to transfer to said memory means.  
     
     
         83 . The image acquisition system of claim  82 , wherein said pixel correction means comprises 
 second memory means for storing a plurality of pre-determined pixel correction values corresponding to each pixel of said image, and    multiplier means for multiplying each pixel of said image by said corresponding pixel correction value, thereby forming a corrected pixel.    
     
     
         84 . The image acquisition system of claim  82 , wherein said pixel correction means is separate from one of the host processor and the host computing system and performs said pixel correction in real time.  
     
     
         85 . The image acquisition system of  claim 60 , wherein a region of interest corresponding to a portion of said image includes a selected number of pixels, further comprising 
 pixel evaluation memory means coupled to image acquisition means for storing a value corresponding to said pixels of said region of interest,and    pre-determined pixel storage means coupled to said image acquisition means for storing a value corresponding to a predetermined number of pixels.    
     
     
         86 . The image acquisition system of claim  85 , further comprising 
 comparing means for comparing said value stored in said pixel evaluation means with said value stored in said predetermined pixel storage means, and    means for generating a match signal when said values are equal, said programmable control means including means for receiving said match signal and for altering said image acquisition parameters.