Method and apparatus for split gate source side injection flash memory cell and array with dedicated erase gates

Abstract

A transistor structure having a dedicated erase gate where the transistor can be used as a memory cell is disclosed. The presently preferred embodiment of the transistor comprises a floating gate disposed on a substrate and having a control gate and an erase gate overlapping said floating gate, with drain and source regions doped on the substrate. By providing a dedicated erase gate, the gate oxide underneath the control gate can be made thinner and can have a thickness that is conducive to the scaling of the transistor. The overall cell size of the transistor remains the same and the program and read operation can remain the same. Both the common source and buried bitline architecture can be used, namely twin well or triple well architectures. A memory circuit using the transistors of the present invention is disclosed as well for flash memory circuit applications.

I claim:  
     
         1 . A method for fabricating a transistor, comprising the steps of: 
 a) providing a substrate;    b) defining a channel region;    c) growing field oxide in defined areas;    d) providing a first insulating layer;    e) depositing a first poly-silicon layer;    f) defining from said first poly-silicon layer a floating gate generally positioned over said channel region;    g) doping a source region;    h) providing a second insulating layer;    i) depositing a second poly-silicon layer;    j) defining a control gate and an erase gate; and    k) doping a drain region.    
     
     
         2 . A method as recited in  claim 1  wherein said control gate is generally positioned on a first side of said floating gate and overlapping said floating gate.  
     
     
         3 . A method as recited in  claim 1  wherein said erase gate is generally positioned on a second side of said floating gate and overlapping said floating gate.  
     
     
         4 . A method as recited in  claim 3  wherein said erase gate is generally positioned on said second side of said floating gate and overlapping said floating gate and said control gate.  
     
     
         5 . A method as recited in  claim 3  wherein said erase gate is generally positioned on said second side of said floating gate and overlapping said floating gate and about flush with said control gate.  
     
     
         6 . A method for fabricating a memory array comprising a plurality of rows and columns of interconnected memory cells wherein the control gates of memory cells in the same rows are connected by a common word-line and the erase gates of the memory cells in the same columns are connected by a common erase line, and the source regions of memory cells in the same rows are connected by a common source line, and drain regions of memory cells in the same columns are connected by a common drain lines, comprising the steps of: 
 a) providing a substrate;    b) defining a channel region;    c) growing field oxide in defined areas;    d) providing a first insulating layer;    e) depositing a first poly-silicon layer;    f) defining from said first poly-silicon layer a floating gate generally positioned over said channel region;    g) doping a source region;    h) providing a second insulating layer;    i) depositing a second poly-silicon layer;    j) defining a control gate and an erase gate; and    k) doping a drain region.    
     
     
         7 . A method as recited in  claim 6  wherein said control gate is generally positioned on a first side of said floating gate and overlapping said floating gate.  
     
     
         8 . A method as recited in  claim 6  wherein said erase gate is generally positioned on a second side of said floating gate and overlapping said floating gate.  
     
     
         9 . A method as recited in  claim 8  wherein said erase gate is generally positioned on said second side of said floating gate and overlapping said floating gate and said control gate.  
     
     
         10 . A method as recited in  claim 8  wherein said erase gate is generally positioned on said second side of said floating gate and overlapping said floating gate and about flush with said control gate.