Thin film transistor and method of fabricating the same

Abstract

A thin film transistor (TFT) and method of fabricating the same. A planarization layer of polymer is formed on the interlayer to reduce short-circuit. The planarization layer further reduces the capacitance of the crossover capacitor and the delay time of the LCD panel using the TFT is therefor minimized. A gate thereof can be design under the data line to increase aperture ratio.

What is claimed is:  
     
         1 . A method of fabricating a TFT, comprising: 
 providing a silicon substrate;    forming a channel region, a first S/D region, and a second S/D region;    forming a gate insulating layer;    forming a gate;    forming an interlayer;    forming a planarization layer;    forming a fist via hole and a second via hole, wherein the first via hole and the second via hole pass through the planarization layer and the interlayer to connect with the first S/D region and the second S/D region, respectively; p 1  depositing and defining a metal layer to form a first S/D region metal line and a second S/D region metal line;    forming a passivation layer;    defining an opening, which passes through the passivation layer to connect with the first S/D region metal line; and    forming a conductive layer.    
     
     
         2 . The method of  claim 1 , wherein the silicon substrate is a quartz substrate.  
     
     
         3 . The method of  claim 1 , wherein the silicon substrate is a glass substrate.  
     
     
         4 . The method of  claim 1 , further comprising: 
 forming a buffer layer above the silicon substrate and below the first S/D region and the second S/D region.    
     
     
         5 . The method of  claim 1 , wherein the gate insulating layer is formed, using Silicon Oxide as material.  
     
     
         6 . The method of  claim 1 , wherein the gate insulating layer is formed by depositing Silicon Nitride, using Plasma Enhanced Chemical Vapor Deposition.  
     
     
         7 . The method of  claim 1 , wherein the planarization layer is formed by coating a layer of polymer.  
     
     
         8 . The method of  claim 7 , wherein the interlayer has a dielectric constant of about 1.5-3.5.  
     
     
         9 . The method of  claim 7 , wherein the polymer is BCB.  
     
     
         10 . The method of  claim 7 , wherein the polymer us PC403.  
     
     
         11 . The method of  claim 2 , wherein the conductive layer is an ITO layer.