Method of forming a bit line and a node contact hole

Abstract

A first and a second dielectric layer are first formed on a substrate of a semiconductor wafer. A landing pad is then formed in the first dielectric layer, and a plurality of openings used in the formation of the bit lines are formed penetrating from the second dielectric layer through to the surface of the first dielectric layer. A conductive layer is then formed to cover the surface of the semiconductor wafer and filling in the openings in the second dielectric layer. An etching back process is then performed to remove portions of the conductive layer so the surface of the conductive layer is lower than that of the second dielectric layer, and the resulting residual conductive layer within the openings form the bit lines. An etching process is performed to form a passivation recess in the second dielectric layer atop each bit line, followed by the formation of a passivation layer in the passivation recess. A third dielectric layer is then formed on the second dielectric layer and covering the passivation layers on the bit lines. Finally, using the passivation layers as hard masks, the node contact hole is formed within both the second and the third dielectric layer.

What is claimed is:  
     
         1 . A method of forming a bit line and a node contact hole on a semiconductor wafer, the semiconductor wafer comprising a substrate, a first dielectric layer positioned on the substrate, a second dielectric layer positioned on the first dielectric layer, and a plurality of openings that are used in the formation of the bit lines and penetrate from the second dielectric layer through to the surface of the first dielectric layer, the method comprising: 
 forming a conductive layer to cover the surface of the semiconductor wafer and filling in the openings in the second dielectric layer;    performing an etching back process to remove portions of the conductive layer so the surface of the conductive layer is lower than that of the second dielectric layer, and the resulting residual conductive layer within the openings form the bit lines;    performing an etching process to form a passivation recess in the second dielectric layer atop each bit line;    forming a passivation layer in the passivation recess;    forming a third dielectric layer on the second dielectric layer and covering the passivation layers on the bit lines; and    using the passivation layers to protect the bit lines and forming the node contact hole within both the second and the third dielectric layers.    
     
     
         2 . The method of  claim 1  wherein the method further comprises a chemical mechanical polishing (CMP) process prior to the etching back process.  
     
     
         3 . The method of  claim 1  wherein the area of the passivation recess opening is larger than the area of the surface of the bit line.  
     
     
         4 . The method of  claim 1  wherein the etching process is an isotropic etching process.  
     
     
         5 . The method of  claim 1  wherein the passivation layer is made up of silicon nitride.  
     
     
         6 . The method of  claim 1  wherein the node contact hole is formed through the third dielectric layer, the second dielectric layer and the first dielectric layer to the surface of the substrate, and makes contact with a source or a drain of a metal-oxide semiconductor (MOS) transistor in the substrate.  
     
     
         7 . The method of  claim 1  wherein the node contact hole is formed through the third dielectric layer and the second dielectric layer, and makes contact with a landing pad in the first dielectric layer.  
     
     
         8 . The method of  claim 1  wherein the passivation layer is used as a stop layer in a self-aligned contact (SAC) etching process during the formation of the node contact hole, and the etching process is continually performed on the portions unprotected by the passivation layer.  
     
     
         9 . A method of protecting a bit line on a semiconductor wafer, the semiconductor wafer comprising a substrate, a first dielectric layer positioned on the substrate, a plurality of bit lines positioned on the surface of the first dielectric layer, and a second dielectric layer covering both the first dielectric layer and the bit lines, the method comprising: 
 using a mask to define patterns of a plurality of passivation recesses on the surface of the second dielectric layer, wherein each of the passivation recesses is positioned atop each of the bit lines, and the area of each passivation recess opening is larger than the area of the surface of each bit line;    performing an etching process to form each of the passivation recesses in the second dielectric layer atop each of the bit lines;    forming a passivation layer in the passivation recess;    forming a third dielectric layer on the second dielectric layer and covering the passivation layers within the bit lines; and    using the passivation layers to protect the bit lines and forming the node contact hole in the second dielectric layer and the third dielectric layer.    
     
     
         10 . The method of  claim 9  wherein the etching process is an isotropic etching process.  
     
     
         11 . The method of  claim 9  wherein the passivation layer is made up of silicon nitride.  
     
     
         12 . The method of  claim 9  wherein the node contact hole is formed through the third dielectric layer, the second dielectric layer and the first dielectric layer to the surface of the substrate, and makes contact with a source or a drain of a metal-oxide semiconductor (MOS) transistor in the substrate.  
     
     
         13 . The method of  claim 9  wherein the node contact hole is formed through the third dielectric layer and the second dielectric layer, and makes contact with a landing pad in the first dielectric layer.  
     
     
         14 . The method of  claim 9  wherein the passivation layer is used as a stop layer in a self-aligned contact (SAC) etching process during the formation of the node contact hole, and the etching process is continually performed on the portions unprotected by the passivation layer.