Semiconductor device and method for manufacturing the same

Abstract

There are provided a semiconductor device a semiconductor device of capable of preventing the deterioration of characteristics of a capacitor of a stacked semiconductor memory device using a ferroelectric or high-dielectric film for the capacitor of the memory cell thereof, without preventing the scale down for high density integration, and a method for manufacturing the same. A semiconductor device according to the present invention includes: a first interlayer insulator film formed as one of a plurality of layers stacked on a semiconductor substrate; a capacitor formed on the first interlayer insulator film, the capacitor having a capacitor bottom electrode, a capacitor top electrode and a capacitor insulator film arranged between the capacitor bottom electrode and the capacitor top electrode; a second interlayer insulator film formed on the first interlayer insulator film, on which the capacitor is formed, the second interlayer insulator film having a surface which has the same level as that of a surface of the capacitor top electrode.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a first interlayer insulator film formed as one of a plurality of layers stacked on a semiconductor substrate;    a capacitor formed on said first interlayer insulator film, said capacitor having a capacitor bottom electrode, a capacitor top electrode and a capacitor insulator film arranged between said capacitor bottom electrode and said capacitor top electrode; and    a second interlayer insulator film formed on said first interlayer insulator film, on which said capacitor is formed, said second interlayer insulator film having a surface which has the same level as that of a surface of said capacitor top electrode.    
     
     
         2 . A semiconductor device as set forth in  claim 1 , wherein said capacitor insulator film is formed of a ferroelectric or a high-dielectric.  
     
     
         3 . A semiconductor device as set forth in  claim 2 , wherein said capacitor insulator film includes PZT (Lead (Pb) Zirconate Titanate).  
     
     
         4 . A semiconductor device as set forth in  claim 1 , wherein one or both of said capacitor bottom electrode and said capacitor top electrode have a stacked structure.  
     
     
         5 . A semiconductor device as set forth in  claim 1 , which further comprises: 
 a contact interconnection layer formed in a contact hole formed in said first and second interlayer insulator films, said contact interconnection layer being electrically connected to a layer below said first interlayer insulator film; and    a capacitor interconnection layer formed in a portion including a part or all of a top surface of said contact interconnection layer on said second interlayer insulator film and a part or all of a surface of said capacitor top electrode.    
     
     
         6 . A semiconductor device as set forth in  claim 5 , wherein a MOS transistor is formed in the surface part of said semiconductor substrate, and said layer below said first interlayer insulator film serves as a gate diffusion layer of said MOS transistor.  
     
     
         7 . A semiconductor device as set forth in  claim 1 , wherein said first interlayer insulator film has a flattened surface, and 
 which further comprises a contact interconnection layer formed in a contact hole formed in said first interlayer insulator film, said contact interconnection layer being electrically connected to a layer below said first interlayer insulator film,    said capacitor being formed in a portion including a part or all of a top surface of said contact interconnection layer on said first interlayer insulator film.    
     
     
         8 . A semiconductor device as set forth in  claim 7 , wherein a MOS transistor is formed in the surface part of said semiconductor substrate, and said layer below said first interlayer insulator film serves as a gate diffusion layer of said MOS transistor.  
     
     
         9 . A semiconductor device comprising: 
 a first interlayer insulator film formed as one of a plurality of layers stacked on a semiconductor substrate;    a capacitor formed on said first interlayer insulator film, said capacitor having a capacitor bottom electrode, a capacitor top electrode and a capacitor insulator film arranged between said capacitor bottom electrode and said capacitor top electrode;    a second interlayer insulator film formed on said first interlayer insulator film, on which said capacitor is formed, said second interlayer insulator film having a surface which is flattened to expose a surface of said capacitor top electrode.    
     
     
         10 . A semiconductor device as set forth in  claim 9 , wherein said capacitor insulator film is formed of a ferroelectric or a high-dielectric.  
     
     
         11 . A semiconductor device as set forth in  claim 10 , wherein said capacitor insulator film includes PZT.  
     
     
         12 . A semiconductor device as set forth in  claim 9 , wherein one or both of said capacitor bottom electrode and said capacitor top electrode have a stacked structure.  
     
     
         13 . A semiconductor device as set forth in  claim 9 , which further comprises: 
 a contact interconnection layer formed in a contact hole formed in said first and second interlayer insulator films, said contact interconnection layer being electrically connected to a layer below said first interlayer insulator film; and    a capacitor interconnection layer formed in a portion including a part or all of a top surface of said contact interconnection layer on said second interlayer insulator film and a part or all of a surface of said capacitor top electrode.    
     
     
         14 . A semiconductor device as set forth in  claim 13 , wherein a MOS transistor is formed in the surface part of said semiconductor substrate, and said layer below said first interlayer insulator film serves as a gate diffusion layer of said MOS transistor.  
     
     
         15 . A semiconductor device as set forth in  claim 13 , wherein said first interlayer insulator film has a flattened surface, and 
 which further comprises a contact interconnection layer formed in a contact hole formed in said first interlayer insulator film, said contact interconnection layer being electrically connected to a layer below said first interlayer insulator film,    said capacitor being formed in a portion including a part or all of a top surface of said contact interconnection layer on said first interlayer insulator film.    
     
     
         16 . A semiconductor device as set forth in  claim 15 , wherein a MOS transistor is formed in the surface part of said semiconductor substrate, and said layer below said first interlayer insulator film serves as a gate diffusion layer of said MOS transistor.  
     
     
         17 . A semiconductor device comprising: 
 a first interlayer insulator film formed as one of a plurality of layers stacked on a semiconductor substrate, on which a MOS transistor for memory cell is formed;    a capacitor formed on said first interlayer insulator film, said capacitor having a capacitor bottom electrode, a capacitor top electrode and a capacitor insulator film arranged between said capacitor bottom electrode and said capacitor top electrode;    a second interlayer insulator film formed on said first interlayer insulator film, on which said capacitor is formed, said second interlayer insulator film having a surface which has the same level as that of a surface of said capacitor top electrode;    a contact interconnection layer formed in a contact hole formed in said first and second interlayer insulator films, said contact interconnection layer being electrically connected to a layer below said first interlayer insulator film; and    a capacitor interconnection layer formed in a portion including a part or all of a top surface of said contact interconnection layer on said second interlayer insulator film and a part or all of a surface of said capacitor top electrode.    
     
     
         18 . A semiconductor device as set forth in  claim 17 , wherein said capacitor insulator film is formed of a ferroelectric or a high-dielectric.  
     
     
         19 . A semiconductor device as set forth in  claim 18 , wherein said capacitor insulator film includes PZT.  
     
     
         20 . A semiconductor device as set forth in  claim 17 , wherein one or both of said capacitor bottom electrode and said capacitor top electrode have a stacked structure.  
     
     
         21 . A semiconductor device comprising: 
 a first interlayer insulator film formed as one of a plurality of layers stacked on a semiconductor substrate, on which a MOS transistor for memory cell is formed;    a capacitor formed on said first interlayer insulator film, said capacitor having a capacitor bottom electrode, a capacitor top electrode and a capacitor insulator film arranged between said capacitor bottom electrode and said capacitor top electrode;    a second interlayer insulator film formed on said first interlayer insulator film, on which said capacitor is formed, said second interlayer insulator film having a surface which is flattened to expose a surface of said capacitor top electrode;    a contact interconnection layer formed in a contact hole formed in said first and second interlayer insulator films, said contact interconnection layer being electrically connected to a layer below said first interlayer insulator film; and    a capacitor interconnection layer formed in a portion including a part or all of a top surface of said contact interconnection layer on said second interlayer insulator film and a part or all of a surface of said capacitor top electrode.    
     
     
         22 . A semiconductor device as set forth in  claim 21 , wherein said capacitor insulator film is formed of a ferroelectric or a high-dielectric.  
     
     
         23 . A semiconductor device as set forth in  claim 22 , wherein said capacitor insulator film includes PZT.  
     
     
         24 . A semiconductor device as set forth in  claim 21 , wherein one or both of said capacitor bottom electrode and said capacitor top electrode have a stacked structure.  
     
     
         25 . A semiconductor device comprising: 
 a first interlayer insulator film formed as one of a plurality of layers stacked on a semiconductor substrate, on which a NOS transistor for memory cell is formed, said first interlayer insulator film has a flattened surface;    a contact interconnection layer formed in a contact hole formed in said first interlayer insulator film, said contact interconnection layer being electrically connected to a gate diffusion layer of said MOS transistor;    a capacitor being formed in a portion including a part or all of a top surface of said contact interconnection layer on said first interlayer insulator film, said capacitor having a capacitor bottom electrode, a capacitor top electrode and a capacitor insulator film arranged between said capacitor bottom electrode and said capacitor top electrode; and    a second interlayer insulator film formed on said first interlayer insulator film, on which said capacitor is formed, said second interlayer insulator film having a surface which has the same level as that of a surface of said capacitor top electrode.    
     
     
         26 . A semiconductor device as set forth in  claim 25 , wherein said capacitor insulator film is formed of a ferroelectric or a high-dielectric.  
     
     
         27 . A semiconductor device as set forth in  claim 26 , wherein said capacitor insulator film includes PZT.  
     
     
         28 . A semiconductor device as set forth in  claim 25 , wherein one or both of said capacitor bottom electrode and said capacitor top electrode have a stacked structure.  
     
     
         29 . A semiconductor device comprising: 
 a first interlayer insulator film formed as one of a plurality of layers stacked on a semiconductor substrate, on which a MOS transistor for memory cell is formed, said first interlayer insulator film has a flattened surface;    a contact interconnection layer formed in a contact hole formed in said first interlayer insulator film, said contact interconnection layer being electrically connected to a gate diffusion layer of said MOS transistor;    a capacitor being formed in a portion including a part or ail of a top surface of said contact interconnection layer on said first interlayer insulator film, said capacitor having a capacitor bottom electrode, a capacitor top electrode and a capacitor insulator film arranged between said capacitor bottom electrode and said capacitor top electrode; and    a second interlayer insulator film formed on said first interlayer insulator film, on which said capacitor is formed, said second interlayer insulator film having a surface which is flattened to expose a surface of said capacitor top electrode.    
     
     
         30 . A semiconductor device as set forth in  claim 29 , wherein said capacitor insulator film is formed of a ferroelectric or a high-dielectric.  
     
     
         31 . A semiconductor device as set forth in  claim 30 , wherein said capacitor insulator film includes PZT.  
     
     
         32 . A semiconductor device as set forth in  claim 29 , wherein one or both of said capacitor bottom electrode and said capacitor top electrode have a stacked structure.  
     
     
         33 . A semiconductor device comprising: 
 a first interlayer insulator film formed as one of a plurality of layers stacked on a semiconductor substrate, on which a MOS transistor for memory cell is formed;    a capacitor formed on said first interlayer insulator film, said capacitor having a capacitor bottom electrode, a capacitor top electrode and a capacitor insulator film arranged between said capacitor bottom electrode and said capacitor top electrode;    a second interlayer insulator film formed on said first interlayer insulator film, on which said capacitor is formed, said second interlayer insulator film having a surface which has the same level as that of a surface of said capacitor top electrode;    a contact interconnection layer formed in a contact hole formed in said first and second interlayer insulator films, said contact interconnection layer being electrically connected to a layer below said first interlayer insulator film; and    a capacitor interconnection layer formed on said second interlayer insulator film so as to be electrically connected to said capacitor top electrode and said contact interconnection layer, said capacitor interconnection layer having a cross-sectional width which is equal to the maximum distance between a side of said capacitor top electrode and a side of said contact interconnection layer or is longer than said maximum distance.    
     
     
         34 . A semiconductor device as set forth in  claim 33 , wherein said capacitor insulator film is formed of a ferroelectric or a high-dielectric.  
     
     
         35 . A semiconductor device as set forth in  claim 34 , wherein said capacitor insulator film includes PZT.  
     
     
         36 . A semiconductor device as set forth in  claim 33 , wherein one or both of said capacitor bottom electrode and said capacitor top electrode have a stacked structure.  
     
     
         37 . A semiconductor device comprising: 
 a first interlayer insulator film formed as one of a plurality of layers stacked on a semiconductor substrate, on which a MOS transistor for memory cell is formed;    a capacitor formed on said first interlayer insulator film, said capacitor having a capacitor bottom electrode, a capacitor top electrode and a capacitor insulator film arranged between said capacitor bottom electrode and said capacitor top electrode;    a second interlayer insulator film formed on said first interlayer insulator film, on which said capacitor is formed, said second interlayer insulator film having a surface which is flattened to expose a surface of said capacitor top electrode;    a contact interconnection layer formed in a contact hole formed in said first and second interlayer insulator films, said contact interconnection layer being electrically connected to a layer below said first interlayer insulator film; and    a capacitor interconnection layer formed on said second interlayer insulator film so as to be electrically connected to said capacitor top electrode and said contact interconnection layer, said capacitor interconnection layer having a cross-sectional width which is equal to the maxim distance between a side of said capacitor top electrode and a side of said contact interconnection layer or is longer than said maximum distance.    
     
     
         38 . A semiconductor device as set forth in  claim 37 , wherein said capacitor insulator film is formed of a ferroelectric or a high-dielectric.  
     
     
         39 . A semiconductor device as set forth in  claim 38 , wherein said capacitor insulator film includes PZT.  
     
     
         40 . A semiconductor device as set forth in  claim 37 , wherein one or both of said capacitor bottom electrode and said capacitor top electrode have a stacked structure.  
     
     
         41 . A method for manufacturing a semiconductor device, comprising: 
 a first step of forming a first interlayer insulator film as one of a plurality of layers stacked on a semiconductor substrate;    a second step of sequentially stacking a bottom electrode layer an insulator film and a top electrode layer on said first interlayer insulator film to process the stacked bottom electrode layer, insulator layer film and top electrode layer in predetermined shapes to form a capacitor comprising a capacitor bottom electrode, a capacitor insulator film and a capacitor top electrode;    a third step of forming a second interlayer insulator film on said first interlayer insulator film, on which said capacitor has been formed; and    a fourth step of flattening said second interlayer insulator film to expose a surface of said capacitor top electrode.    
     
     
         42 . A method for manufacturing a semiconductor device as set forth in  claim 41 , wherein said fourth step is carried out by the chemical mechanical polishing (CMP).  
     
     
         43 . A method for manufacturing a semiconductor device as set forth in  claim 41 , wherein said fourth step is carried out by the CMP and etching.  
     
     
         44 . A method for manufacturing a semiconductor device as set forth in  claim 41 , which further comprises: 
 a fifth step of forming a contact hole in said first and second interlayer insulator film to form a contact interconnection layer in said contact hole, said contact interconnection layer being electrically connected to a layer below said first interlayer insulator film; and    a sixth step of forming a capacitor interconnection layer in a portion including a part or all of a top surface of said contact interconnection layer on said second interlayer insulator film and a part or all of a surface of said capacitor top electrode.