FM composite signal processor

Abstract

A signal processor for amplitude and frequency limiting of a multiplex FM composite signal is described. To maximize the amount of available bandwidth and minimize the generated distortion, the disclosed signal processor employs multiple low-distortion amplifying and clipping subsystems. The subsystems include a stereophonic pilot signal protection circuit which protects the 19 khz pilot signal from the composite FM signal processing, an adjustable limiting circuit, and an adjustable dual low-pass filter/overshoot compensation circuit.

I claim:  
     
         1 . A signal processor for use in preparation of a modulated signal to be broadcast comprising: 
 a modulated signal; and,    a clipping amplifier comprising: 
 a first low-pass filter, having a first transfer function, receiving the modulated signal;  
 a first overshoot compensator removing any modulation above a predetermined maximum modulation created by said first low-pass filter.  
   
     
     
         2 . A signal processor according to  claim 1 , further comprising: 
 a second low-pass filter, having a second transfer function, receiving the output from said first overshoot compensator;    a second overshoot compensator removing any modulation above said predetermined maximum modulation created by said second low pass filter.    
     
     
         3 . A signal processor according to  claim 1 , further comprising: 
 a first circuit receiving an input signal having a pilot subcarrier and the modulated signal, said first circuit separating the pilot subcarrier from the input signal and outputting the modulated signal to said clipping amplifier, said first circuit recombining the pilot subcarrier with the output of said clipping amplifier.    
     
     
         4 . A signal processor according to  claim 2 , further comprising: 
 a first circuit receiving an input signal having a pilot subcarrier and the modulated signal, said first circuit separating the pilot subcarrier from the input signal and outputting the modulated signal to said clipping amplifier, said first circuit recombining the pilot subcarrier with the output of said clipping amplifier.    
     
     
         5 . A signal processor according to  claim 1 , said first overshoot compensator comprising: 
 a clipper receiving the output of said first low-pass filter;    a difference amplifier outputting the difference between the output of said first low-pass filter and said clipper;    a summing circuit combining the output of said low-pass filter and said difference amplifier.    
     
     
         6 . A signal processor according to  claim 2 , said first overshoot compensator comprising: 
 a first clipper receiving the output of said first low-pass filter;    a first difference amplifier outputting the difference between the output of said first low-pass filter and said first clipper;    a first summing circuit combining the output of said low-pass filter and said first difference amplifier.    
     
     
         7 . A signal processor according to  claim 6 , said second overshoot compensator comprising: 
 a second clipper receiving the output of said second low-pass filter;    a second difference amplifier outputting the difference between the output of said second low-pass filter and said second clipper;    a second summing circuit combining the output of said second low-pass filter and said second difference amplifier.    
     
     
         8 . A signal processor according to  claim 5 , said clipper clipping through amplifying the output of said first low-pass filter to a predetermined high voltage and to a predetermined low voltage.  
     
     
         9 . A signal processor according to  claim 8 , further comprising: 
 a compensator bias adjustment;    a voltage follower receiving the output of said compensator bias adjustment and outputting said predetermined high voltage;    an inverting amplifier receiving said predetermined high voltage and outputting said predetermined low voltage;    a symmetry adjusting circuit across said inverting amplifier adjusting the balance between said predetermined high voltage and said predetermined low voltage.    said predetermined high voltage and said predetermined low voltage    
     
     
         10 . A signal processor according to  claim 6 , said first clipper clipping through amplifying the output of said first low-pass filter to a first predetermined high voltage and to a first predetermined low voltage.  
     
     
         11 . A signal processor according to  claim 10 , further comprising: 
 a first compensator bias adjustment;    a first voltage follower receiving the output of said first compensator bias adjustment and outputting said first predetermined high voltage;    a first inverting amplifier receiving said first predetermined high voltage and outputting said first predetermined low voltage;    a first symmetry adjusting circuit across said first inverting amplifier adjusting the balance between said first predetermined high voltage and said first predetermined low voltage.    
     
     
         12 . A signal processor according to  claim 7 , said second clipper clipping through amplifying the output of said second low-pass filter to a second predetermined high voltage and to a second predetermined low voltage.  
     
     
         13 . A signal processor according to  claim 12 , further comprising: 
 a second compensator bias adjustment;    a second voltage follower receiving the output of said second compensator bias adjustment and outputting said second predetermined high voltage;    a second inverting amplifier receiving said second predetermined high voltage and outputting said second predetermined low voltage;    a second symmetry adjusting circuit across said second inverting amplifier adjusting the balance between said second predetermined high voltage and said second predetermined low voltage.    
     
     
         14 . A signal processor according to  claim 1 , further comprising: 
 an unlimited modulated signal;    a limiter circuit for limiting the modulations of the unlimited modulated signal to a predetermined maximum modulation and outputting said modulated signal;    
     
     
         15 . A signal processor according to  claim 2 , further comprising: 
 a delay equalizer connected between said second low pass filter and said second overshoot compensator.    
     
     
         16 . A signal processor according to  claim 1 , further comprising: 
 a delay equalizer connected between said first low pass filter and said first overshoot compensator.    
     
     
         17 . In a signal processor preparing a complex signal to be broadcast comprising, a circuit for protecting a pilot signal in a complex signal comprising: 
 separating means for separating out the pilot signal;    inverting means, receiving the pilot signal from said separating means, for reversing the phase of the pilot signal;    a summing circuit combining the complex signal with the output of said inverting means to remove the pilot signal from the complex signal;    processing means for processing the output from said summing circuit;    restoring means for restoring the pilot signal with the output of the processing means.    
     
     
         18 . A circuit according to  claim 17 , said separating means comprising: 
 a first bandpass filter, having a first transfer function, receiving the complex signal;    a limiter circuit receiving the output of said first bandpass filter; and,    a second bandpass filter, having a second transfer function, receiving the output of said limiter circuit and outputting the pilot signal to said inverting means.    
     
     
         19 . A circuit according to  claim 17 , said circuit further comprising: 
 adjusting means connected between said inverting means and summing circuit for adjusting the phase reversed pilot signal.    
     
     
         20 . In a signal processor preparing a modulated signal to be broadcast comprising, a circuit for limiting the modulation of a modulated signal comprising: 
 a clipper amplifier receiving the modulated signal, said clipper operating between a predetermined high voltage and a predetermined low voltage;    adjusting means adjusting the predetermined high voltage and the predetermined low voltage.    
     
     
         21 . A circuit according to  claim 20 , said adjusting means comprising: 
 setting means for setting one of the predetermined high voltage and the predetermined low voltage;    an inverting circuit for inverting said one of the predetermined high voltage and the predetermined low voltage and outputting the other one of the predetermined high voltage and the predetermined low voltage; and,    a balance circuit connected across said inverting circuit adjusting the balance between the predetermined high voltage and the predetermined low voltage.    
     
     
         22 . A signal processor according to  claim 2 , wherein said second overshoot compensator is adjusted differently from said first overshoot compensator.  
     
     
         23 . A signal processor according to  claim 2 , wherein said second transfer function of said second low-pass filter is different from said first transfer function of said first low-pass filter.  
     
     
         24 . A circuit according to  claim 18 , wherein said second transfer function of said second bandpass filter is different from said first transfer function of said first bandpass filter.