Two-exposure phase shift photolithography with improved inter-feature separation

Abstract

A method of double-exposure photolithography of a semiconductor wafer in the manufacture of integrated circuits is disclosed. The two exposures of the same positive photoresist layer are carried out using a binary photomask ( 25 ) having chrome regions ( 22 ) that define non-critical dimension features ( 6 c ) and also serve as protection for phase shift exposure of critical dimension features ( 6 g ). The phase shift photomask ( 23 ) includes apertures 20 0 , 20 π , that expose the sides of the critical dimension feature ( 6 g ) with opposite phase light. The phase shift photomask ( 23 ) also includes an additional aperture ( 30 ) for double exposure of a region exposed by the binary photomask, for example as between a non-critical dimension feature ( 6 c ) and the end of a critical dimension feature ( 6 g ). According to another disclosed feature, orthogonal overlapping chrome regions ( 34, 36 ), each of critical dimension width (w 34 , w 36 ), are provided on the binary and phase shift photomasks ( 35, 33 ), to define a feature by way of their intersection.

We claim:  
     
         1 . A method of fabricating an integrated circuit, comprising the steps of: 
 applying a photosensitive material at a surface of a semiconductor wafer;    exposing the photosensitive material to electromagnetic energy through a binary photomask, the binary photomask having a plurality of opaque regions at a surface thereof to block selected locations of the photosensitive material from exposure to the electromagnetic energy, the plurality of opaque regions including first and second opaque regions disposed near one another and defining a first aperture therebetween through which the photosensitive material is exposed to the electromagnetic energy; and    exposing the photosensitive material to electromagnetic energy at a selected wavelength through a phase shift photomask, the phase shift photomask having an opaque film at a surface thereof in which a plurality of apertures are formed to define locations at which the photosensitive material is exposed to the electromagnetic energy, the plurality of apertures including first and second phase shift apertures separated from one another on the photomask by a first opaque region of the opaque film, the first phase shift aperture constructed to transmit electromagnetic energy at substantially an opposite phase from the electromagnetic energy transmitted by the second phase shift aperture, and the plurality of apertures also including a third aperture in the opaque film separated from the first and second phase shift apertures;    wherein the binary photomask and the phase shift photomasks are aligned in their respective exposing steps so that the first opaque region of the phase shift photomask corresponds to a first integrated circuit location that also corresponds to the first opaque region of the binary photomask;    and wherein the binary photomask and the phase shift photomasks are aligned in their respective exposing steps so that the third aperture of the phase shift mask corresponds to a second integrated circuit location that also corresponds to the first aperture of the binary photomask.    
     
     
         2 . The method of  claim 1 , wherein the applying step applies the photosensitive material over a conductive layer at the surface of the wafer; 
 and further comprising: 
 after the exposing steps, developing the photosensitive material to remove portions thereof defined in the exposing steps, to expose portions of the conductive layer; and  
 after the developing step, etching the exposed portions of the conductive layer.  
   
     
     
         3 . The method of  claim 2 , wherein the developing step removes portions of the photosensitive material that were exposed to electromagnetic energy in the exposing steps.  
     
     
         4 . The method of  claim 3 , wherein the conductive layer comprises polysilicon.  
     
     
         5 . The method of  claim 4 , wherein the first integrated circuit location corresponds to a polysilicon gate electrode.  
     
     
         6 . The method of  claim 5 , wherein the second opaque region of the binary photomask corresponds to a polysilicon conductor.  
     
     
         7 . The method of  claim 6 , wherein the conductive layer comprising polysilicon is disposed over an active region of the integrated circuit wafer and also over a field oxide structure of the integrated circuit wafer; 
 wherein the first integrated circuit location corresponds to a polysilicon gate electrode overlying the active region;    and wherein the second opaque region of the binary photomask corresponds to a polysilicon conductor overlying the field oxide structure.    
     
     
         8 . The method of  claim 7 , wherein the second integrated circuit location corresponds to a location overlying the field oxide structure.  
     
     
         9 . The method of  claim 1 , wherein the step of exposing the photosensitive material to electromagnetic energy at a selected wavelength through the phase shift photomask is performed after the step of exposing the photosensitive material to electromagnetic energy through the binary photomask.  
     
     
         10 . The method of  claim 1 , wherein the step of exposing the photosensitive material to electromagnetic energy through the binary photomask is performed after the step of exposing the photosensitive material to electromagnetic energy at a selected wavelength through the phase shift photomask.  
     
     
         11 . The method of  claim 1 , wherein the plurality of opaque regions of the binary photomask also includes a third opaque region, having a rectangular shape with a first dimension longer than a second dimension; 
 wherein the plurality of apertures of the phase shift mask also define a second opaque region having a rectangular shape with a first dimension longer than a second dimension;    and wherein the binary photomask and the phase shift photomask are aligned in their respective exposing steps to define a third integrated circuit location corresponding to the intersection of the third opaque region of the binary photomask and the second opaque region of the phase shift mask, the third opaque region of the binary photomask and the second opaque region of the phase shift mask being aligned orthogonal to one another so that the third integrated circuit location has a size defined by the second dimension of each of the third opaque region of the binary photomask and the second opaque region of the phase shift mask.    
     
     
         12 . A set of photomasks for photolithographic patterning of a layer of an integrated circuit, comprising: 
 a binary photomask having a plurality of opaque regions at a surface thereof, the plurality of opaque regions including first and second opaque regions disposed near one another and defining a first aperture therebetween;    a phase shift photomask having an opaque film at a surface thereof in which a plurality of apertures are formed, the plurality of apertures including first and second phase shift apertures separated from one another on the photomask by a first opaque region of the opaque film, the first and second phase shift apertures constructed to transmit electromagnetic energy at substantially opposite phases relative to one another, and the plurality of apertures also including a third aperture in the opaque film separated from the first and second phase shift apertures;    wherein the first opaque region of the phase shift photomask corresponds to a first integrated circuit location that also corresponds to the first opaque region of the binary photomask;    and wherein the third aperture of the phase shift mask corresponds to a second integrated circuit location that also corresponds to the first aperture of the binary photomask.    
     
     
         13 . The set of photomasks of  claim 12 , wherein the plurality of opaque regions of the binary photomask also includes a third opaque region, having a rectangular shape with a first dimension longer than a second dimension; 
 wherein the plurality of apertures of the phase shift mask also define a second opaque region having a rectangular shape with a first dimension longer than a second dimension;    and wherein the intersection of the third opaque region of the binary photomask and the second opaque region of the phase shift mask define a third integrated circuit location, the third opaque region of the binary photomask and the second opaque region of the phase shift mask being aligned orthogonal to one another so that the third integrated circuit location has a size defined by the second dimension of each of the third opaque region of the binary photomask and the second opaque region of the phase shift mask.