High-g mounting arrangement for electronic chip carrier

Abstract

A chip carrier is coupled to a printed circuit board by leads so that the chip carrier stands off from the printed circuit board. A spacer is provided between the chip carrier and the printed circuit board. The spacer reduces g forces on the leads.

What is claimed is:  
     
         1 . A mounting arrangement comprising: 
 a chip carrier;    a mounting structure; and,    a spacer between the chip carrier and the mounting structure, wherein the spacer has dimensions so as to transfer g forces from the chip carrier to the mounting structure.    
     
     
         2 . The mounting arrangement of  claim 1  wherein the chip carrier and the spacer are both ceramic.  
     
     
         3 . The mounting arrangement of  claim 1  further comprising a first adhesive layer that bonds the spacer to the chip carrier and a second adhesive layer that bonds the spacer to the mounting structure.  
     
     
         4 . The mounting arrangement of  claim 3  wherein the first adhesive layer is arranged to strengthen and stiffen the chip carrier.  
     
     
         5 . The mounting arrangement of  claim 3  wherein the spacer has a first coefficient of thermal expansion, wherein at least one of the first and second adhesive layers has a second coefficient of thermal expansion, and wherein the first coefficient of thermal expansion is less that the second coefficient of thermal expansion.  
     
     
         6 . The mounting arrangement of  claim 3  wherein the chip carrier and the spacer are both ceramic.  
     
     
         7 . The mounting arrangement of  claim 3  wherein the first and second adhesive layers are epoxy.  
     
     
         8 . The mounting arrangement of  claim 7  wherein the chip carrier and the spacer are both ceramic.  
     
     
         9 . The mounting arrangement of  claim 8  wherein the ceramic of the spacer has a first coefficient of thermal expansion, wherein the epoxy has a second coefficient of thermal expansion, and wherein the first coefficient of thermal expansion is less that the second coefficient of thermal expansion.  
     
     
         10 . The mounting arrangement of  claim 1  wherein the spacer is ceramic.  
     
     
         11 . The mounting arrangement of  claim 1  wherein the mounting structure is a printed circuit board.  
     
     
         12 . A mounting arrangement comprising: 
 a chip carrier;    a mounting structure;    leads that couple the chip carrier to the mounting structure so that the chip carrier stands off from the mounting structure; and,    a spacer between the chip carrier and the mounting structure, wherein the spacer reduces g forces on the leads.    
     
     
         13 . The mounting arrangement of  claim 12  wherein the chip carrier and the spacer are both ceramic.  
     
     
         14 . The mounting arrangement of  claim 12  further comprising a first adhesive layer that bonds the spacer to the chip carrier, and a second adhesive layer that bonds the spacer to the mounting structure.  
     
     
         15 . The mounting arrangement of  claim 14  wherein the first adhesive layer is arranged to strengthen and stiffen the chip carrier.  
     
     
         16 . The mounting arrangement of  claim 14  wherein the spacer and the first and second adhesive layers are selected so that thermal expansions of the spacer and the first and second adhesive layers substantially match thermal expansion of the leads.  
     
     
         17 . The mounting arrangement of  claim 14  wherein the spacer has a first coefficient of thermal expansion CTE 1 , wherein the leads have a second coefficient of thermal expansion CTE 2 , wherein the first and second adhesive layers have a third coefficient of thermal expansion CTE 3 , and wherein CTE 1 <CTE 2 <CTE 3 .  
     
     
         18 . The mounting arrangement of  claim 14  wherein the chip carrier and the spacer are both ceramic.  
     
     
         19 . The mounting arrangement of  claim 14  wherein the first and second adhesive layers are epoxy.  
     
     
         20 . The mounting arrangement of  claim 19  wherein the chip carrier and the spacer are both ceramic.  
     
     
         21 . The mounting arrangement of  claim 20  wherein the ceramic of the spacer has a first coefficient of thermal expansion CTE 1 , wherein the leads have a second coefficient of thermal expansion CTE 2 , wherein the epoxy has a third coefficient of thermal expansion CTE 3 , and wherein CTE 1 <CTE 2 <CTE 3 .  
     
     
         22 . The mounting arrangement of  claim 12  wherein the mounting structure is a printed circuit board.  
     
     
         23 . The mounting arrangement of  claim 12  wherein the spacer is ceramic.  
     
     
         24 . The mounting arrangement of  claim 12  wherein the spacer is selected so that thermal expansion of the spacer substantially matches thermal expansion of the leads.  
     
     
         25 . A method of mounting a chip carrier to a mounting structure comprising: 
 bonding a spacer to the chip carrier; and,    bonding the spacer to the mounting structure, wherein the spacer is arranged to transfer g forces from the chip carrier to the mounting structure.    
     
     
         26 . The method of  claim 25  wherein the chip carrier and the spacer are both ceramic.  
     
     
         27 . The method of  claim 25  wherein the bonding of the spacer to the chip carrier comprises bonding the spacer to the chip carrier using a first adhesive layer, and wherein the bonding of the spacer to the mounting structure comprises bonding the spacer to the mounting structure using a second adhesive layer.  
     
     
         28 . The method of  claim 27  wherein the first adhesive layer is arranged to strengthen and stiffen the chip carrier.  
     
     
         29 . The method of  claim 27  further comprising coupling the chip carrier to the mounting structure with electrical leads, wherein the spacer and the first and second adhesive layers are selected so that thermal expansions of the spacer and the first and second adhesive layers substantially match thermal expansion of the electrical leads.  
     
     
         30 . The method of  claim 27  further comprising coupling the chip carrier to the mounting structure with electrical leads, wherein the spacer has a first coefficient of thermal expansion CTE 1 , wherein the leads have a second coefficient of thermal expansion CTE 2 , wherein the first and second adhesive layers have a third coefficient of thermal expansion CTE 3 , and wherein CTE 1 <CTE 2 <CTE 3 .  
     
     
         31 . The method of  claim 27  wherein the chip carrier and the spacer are both ceramic.  
     
     
         32 . The method of  claim 27  wherein the first and second adhesive layers are epoxy.  
     
     
         33 . The method of  claim 32  wherein the chip carrier and the spacer are both ceramic.  
     
     
         34 . The method of  claim 25  wherein the mounting structure is a printed circuit board.  
     
     
         35 . The method of  claim 25  wherein the spacer is ceramic.  
     
     
         36 . An assembly comprising: 
 a chip carrier;    a mounting structure;    leads electrically coupled to the chip carrier and to the mounting structure; and,    a force diverter mechanically coupled to the chip carrier and to the mounting structure, wherein the force diverter is arranged to divert force generated by the chip carrier from the leads and to the mounting structure.    
     
     
         37 . The assembly of  claim 36  wherein the force diverter is between the chip carrier and the mounting structure.  
     
     
         38 . The assembly of  claim 37  wherein the force diverter is selected so that thermal expansion of the force diverter substantially matches thermal expansion of the leads.  
     
     
         39 . The assembly of  claim 36  wherein the force diverter is selected so that thermal expansion of the force diverter substantially matches thermal expansion of the leads.