Semiconductor device having a contact window and fabrication method thereof

Abstract

Semiconductor devices having a contact window and fabrication methods thereof are provided. A lower dielectric layer, conductive patterns and an upper dielectric layer are formed sequentially on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than that of the upper dielectric layer. The upper dielectric layer and the lower dielectric layer are patterned by anisotropic etching to form a trench without exposing the semiconductor substrate. The resultant structure is subject to isotropic etching to expose the substrate and to form a contact window having a wider width in a lower region than in an upper region without damaging the semiconductor substrate.

What is claimed is:  
     
         1 . A method of fabricating a semiconductor device comprising: 
 forming a lower dielectric layer on a semiconductor substrate;    forming an upper dielectric layer on the lower dielectric layer;    anisotropically etching the upper dielectric layer and the lower dielectric layer to form a trench therein, the trench passing through the upper dielectric layer and having a depth less than a combined thickness of the upper dielectric layer and the lower dielectric layer; and    isotropically etching the lower dielectric layer exposed by the trench to form a contact window, wherein a width of a lower region of the contact window is wider than a width of an upper region of the contact window.    
     
     
         2 . The method of  claim 1 , wherein the anisotropic etching is performed using a dry etching process and the isotropic etching is performed using a wet etching process.  
     
     
         3 . The method of  claim 1 , wherein the lower dielectric layer comprises a material layer having a higher etch rate than the upper dielectric layer.  
     
     
         4 . The method of  claim 3 , wherein the lower dielectric layer comprises one selected from the group consisting of a BPSG layer, an SOG layer and an O 3 -TEOS layer and the upper dielectric layer comprises one of selected from the group consisting of a USG layer, an HDP layer and O 2 -TEOS layer.  
     
     
         5 . The method of  claim 1 , wherein forming the lower dielectric layer comprises: 
 forming a first dielectric layer on the semiconductor substrate; and    forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has a lower etch rate than the first dielectric layer during the isotropic etching.    
     
     
         6 . The method of  claim 5 , wherein the first dielectric layer comprises one selected from the group consisting of a BPSG layer, an SOG layer and an O 3 -TEOS layer and the second dielectric layer comprises one selected from the group consisting of a USG layer, an HDP layer and an O 2 -TEOS layer.  
     
     
         7 . The method of  claim 1 , wherein the etch rate of the lower dielectric layer increases in a direction toward the substrate.  
     
     
         8 . The method of  claim 7 , wherein the lower dielectric layer is formed by a process in which a flow rate of O 3  gas decreases and a flow rate of O 2  gas increases.  
     
     
         9 . The method of  claim 1 , wherein the anisotropic etching comprises forming a polymer with a thickness of 100-500 Å on a sidewall of the trench, and wherein the polymer suppresses the isotropic etching.  
     
     
         10 . The method of  claim 9 , wherein the isotropic etching is performed by using a mixture including a DI water, NH 4 F and HF, wherein A volume percentage of the HF in the mixture is approximately 0.1-0.4%.  
     
     
         11 . The method of  claim 1  further comprises forming a spacer on a sidewall of the trench.  
     
     
         12 . The method of  claim 11  further comprises forming a capping layer on the upper dielectric layer.  
     
     
         13 . The method of  claim 11 , wherein the spacer is made of a material selected from the group consisting of polycrystalline silicon, silicon nitride and silicon oxynitride.  
     
     
         14 . The method of  claim 12 , wherein the capping layer is made of a material selected from the group consisting of polycrystalline silicon, silicon nitride and silicon oxynitride.  
     
     
         15 . A method of fabricating a semiconductor device comprising: 
 forming a first dielectric layer on a semiconductor substrate;    forming a second dielectric layer on the first dielectric layer, wherein the first dielectric layer comprises a material having a higher isotropic etch rate than that of the second dielectric layer;    anisotropically etching the first dielectric layer and the second dielectric layer to form a trench, the trench passing through the second dielectric layer; and    isotropically etching the first dielectric layer to form a contact window such that a width of a lower region of the contact window is wider than that of an upper region of the contact window.    
     
     
         16 . The method of  claim 15 , which further comprises forming a plurality of conductive patterns disposed between the second dielectric layer and the upper dielectric layer.  
     
     
         17 . The method of  claim 15 , wherein the first dielectric layer is formed of one selected from the group consisting of a BPSG layer, an SOG layer and an O 3 -TEOS layer and the second dielectric layer is formed of one selected from the group consisting of an USG layer, an HDP oxide layer and an O 2 -TEOS layer.  
     
     
         18 . A method of fabricating a semiconductor device comprising: 
 forming a dielectric layer on a semiconductor substrate, wherein the dielectric layer comprises a layer having an etch rate that increases in a direction toward the substrate;    anisotropically etching a portion of the dielectric layer; and    isotropically etching the dielectric layer to form a contact window.    
     
     
         19 . The method of  claim 18 , wherein the contact window has a width of a lower region of the contact window is wider than that of an upper region of the contact window.  
     
     
         20 . The method of  claim 18 , wherein the layer is formed by a process in which a flow rate of O 3  gas decreases and a flow rate of O 2  gas increases.  
     
     
         21 . A semiconductor device comprising: 
 a dielectric layer on a semiconductor substrate;    a contact window passing through the dielectric layer;    an upper region of the contact window having a sidewall substantially perpendicular to the substrate; and    a lower region of the contact window having a width that increases in a direction toward the substrate.    
     
     
         22 . The semiconductor device of  claim 21  further comprises a plurality of conductive patterns disposed between the second dielectric layer and the upper dielectric layer, wherein the conductive patterns are spaced apart from the contact window.  
     
     
         23 . The semiconductor device of  claim 22 , wherein one of the plurality of conductive patterns is spaced apart from another one of the plurality of conductive patterns by a selected distance, and a bottommost width of the contact window is wider than the selected distance.  
     
     
         24 . A semiconductor device comprising: 
 a dielectric layer on a semiconductor substrate;    a contact window passing through the dielectric layer;    an upper region of the contact window having a sidewall substantially perpendicular to the substrate;    a lower region of the contact window having a wider width than that of the upper region of the contact window; and    a spacer on the sidewall.    
     
     
         25 . The semiconductor device of  claim 24  further comprises a plurality of conductive patterns in the dielectric layer, wherein the plurality of conductive patterns is spaced apart from the contact window.  
     
     
         26 . The semiconductor device of  claim 25 , wherein one of the plurality of conductive patterns is spaced apart from another one of the plurality of conductive patterns with a selected distance, and a bottommost width of the contact window is wider than the selected distance.  
     
     
         27 . The semiconductor device of  claim 24  further comprises a capping layer on the dielectric layer.  
     
     
         28 . The semiconductor device of  claim 24 , wherein the spacer is made of a material selected from the group consisting of polycrystalline silicon, silicon nitride and silicon oxynitride.  
     
     
         29 . The semiconductor device of  claim 27 , wherein the capping layer is made from a material selected of the group consisting of polycrystalline silicon, silicon nitride and silicon oxynitride.  
     
     
         30 . A semiconductor device comprising: 
 an interlayer dielectric layer on a semiconductor substrate, wherein the interlayer dielectric layer comprises a first dielectric layer, a second dielectric layer and a upper dielectric layer;    a contact window passing through the interlayer dielectric layer, wherein a lower region of the contact window has a wider width than that of an upper region of the contact window; and    a plurality of conductive patterns intervening between the second dielectric layer and the upper dielectric layer, wherein the conductive patterns are spaced apart from the contact window.    
     
     
         31 . The semiconductor device of claim  30 , wherein one of the plurality of conductive patterns is spaced apart from another one of the plurality of conductive patterns with a selected distance, and a bottommost width of the contact window is wider than the distance.  
     
     
         32 . The semiconductor device of claim  30 , wherein a width of the contact window in the upper dielectric layer is substantially the same as a width of the contact window in the second dielectric layer.