CMOS image sensor with complete pixel reset without kTC noise generation

Abstract

In an image sensing array, the structure of the image sensor pixel is based on a vertical punch through transistor with a junction gate surrounding its source and connected to it, the junction gate being further surrounded by an MOS gate. The new pixel has a large conversion gain, high dynamic range, blooming protection, and low dark current. It senses charge nondestructively with a complete charge removal, which avoids generation of kTC noise. The pixel fabrication is compatible with CMOS processing that includes two metal layers. The array also includes the pixel reset through column sense lines, polysilicon field plate in the image-sensing area for improved pixel isolation, denser pixel packing, and either n-channel or p-channel addressing transistor.

What is claimed:  
     
         1 . A CMOS Active Pixel Sensor having pixels with complete charge removal during pixel reset, comprising: 
 an array of CMOS sensor pixels on a substrate; and    a vertical punch through transistor, having a source near the surface of the substrate, incorporated into the array of CMOS sensor pixels.    
     
     
         2 . The sensor according to  claim 1 , wherein at least one pixel of the array consists of an addressing transistor and a vertical punch through transistor.  
     
     
         3 . The sensor according to  claim 1 , wherein the source of the said vertical punch through transistor is located substantially near the surface of the semiconductor substrate of the sensor array, and is connected to a first junction gate region surrounding the source and doped by the same impurity type as the source and as the substrate.  
     
     
         4 . The sensor according to  claim 3 , wherein the first junction gate region has an underlying buried layer of opposite polarity doping than the source and the substrate.  
     
     
         5 . The sensor according to  claim 3 , wherein the said first junction gate region is surrounded by a second MOS gate region separated from the substrate by a dielectric layer.  
     
     
         6 . The sensor according to  claim 5 , wherein said second MOS gate region is biased to form a potential barrier to prevent charge accumulated under the first junction gate from escaping into surrounding semiconductor regions when the first junction gate is biased at a high bias level.  
     
     
         7 . The sensor according to  claim 6 , wherein said potential barrier is positioned to allow charge accumulated under the first junction gate to escape into the surrounding semiconductor regions when the first junction gate is biased at a low bias level.  
     
     
         8 . The sensor according to  claim 5 , wherein the second MOS gate region contains an n-type buried layer placed in a p type silicon substrate that is extending and contiguous with a n-type layer located under the first junction gate; and 
 the second MOS gate region contains a threshold adjusting implant located in the substrate near a silicon-silicon dioxide interface.    
     
     
         9 . The sensor according to  claim 6 , wherein the semiconductor region in the substrate surrounding the second MOS gate region is n-well.  
     
     
         10 . The sensor according to  claim 9 , wherein the said n-well contains at least one p-channel transistor.  
     
     
         11 . The sensor according to  claim 10 , the sensor being formed on a semiconductor substrate, and wherein the n-well that is located in the semiconductor substrate which is overlapped by a polysilicon layer everywhere except for the regions that contain the p type transistors; and the polysilicon layer is isolated from the substrate by a suitable dielectric layer except for small openings that connect the polysilicon layer to the substrate and the n-well.  
     
     
         12 . The sensor according to  claim 8 , wherein a substrate region surrounding the MOS gate region includes n+ drain adjacent and contiguous with a buried channel region, said buried channel region being located in the substrate under the MOS gate, the said n+ drain region being further surrounded by a p-type substrate.  
     
     
         13 . The Sensor according to  claim 12 , including a cell-addressing transistor placed in the p-type substrate.  
     
     
         14 . The Sensor according to  claim 13 , where the vrll-addressing transistor is n-channel.  
     
     
         15 . A CMOS Active Pixel Sensor having pixels with complete charge removal during pixel reset, comprising: 
 an array of CMOS sensor pixels on a substrate;    a vertical punch through transistor, having a source near the surface of the substrate, incorporated into the array of CMOS sensor pixels;    a junction gate surrounding the source of the transistor; and    an MOS gate surrounding the junction gate and separated from the substrate by a dielectric layer.    
     
     
         16 . A CMOS Active Pixel Sensor having pixels with complete charge removal during pixel reset, comprising: 
 an array of CMOS sensor pixels on a substrate;    a vertical punch through transistor, having a source near the surface of the substrate, incorporated into the array of CMOS sensor pixels; and    peripheral CMOS circuits for addressing the pixels and read-out of the signals.