Visual instruction set for CPU with integrated graphics functions

Abstract

An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized graphics instructions and accompanying hardware for executing them are disclosed to optimize the execution of graphics instruction with minimal additional hardware for a general purpose CPU.

What is claimed is:  
     
         1 . A microprocessor for performing both graphics and non-graphics operations, comprising: 
 a first source register;    a second source register;    a destination register;    multiplier logic having first and second inputs coupled to two of said registers and being configured to perform a partitioned multiply on a plurality of values in each of said two registers in response to a multiply/add Opcode; and    an adder having a first input coupled to a third one of said registers and a second input coupled to an output of said multiplier logic, and being configured to perform a partitioned addition of a plurality of values in said third register with a plurality of values output from said multiplier in response to said multiply/add Opcode.    
     
     
         2 . The microprocessor of  claim 1  further comprising a mask register for indicating which partitioned fields of at least one of said registers are to be operated on.  
     
     
         3 . A microprocessor for performing both graphics and non-graphics operations, comprising: 
 a first source register;    a second source register;    a destination register;    multiplier logic having first and second inputs coupled to two of said registers and being configured to perform a partitioned multiply on a plurality of values in each of said two registers in response to a multiply/subtract Opcode; and    a subtractor having a first input coupled to a third one of said registers and a second input coupled to an output of said multiplier logic, and being configured to perform a partitioned subtraction between a plurality of values in said third register and a plurality of values output from said multiplier in response to said multiply/subtract Opcode.    
     
     
         4 . The microprocessor of  claim 3  further comprising a mask register for indicating which partitioned fields of at least one of said registers are to be operated on.  
     
     
         5 . A computer readable memory accessible by a microprocessor for performing both graphics and non-graphics operations, comprising: 
 an OPcode instruction configured to cause said microprocessor to perform a partitioned multiply of a plurality of first register values packed into a first register by a plurality of second register values packed into a second register to provide a plurality of multiply results, and a partitioned add of said multiply results to a plurality of third register values packed into a third register.    
     
     
         6 . The memory of  claim 5  further comprising an OPcode instruction for setting a mask indicating which partitioned fields of at least one of said registers are to be operated on.  
     
     
         7 . A computer readable memory accessible by a microprocessor for performing both graphics and non-graphics operations, comprising: 
 an OPcode instruction configured to cause said microprocessor to perform a partitioned multiply of a plurality of first register values packed into a first register by a plurality of second register values packed into a second register to provide a plurality of multiply results, and a partitioned subtract between said multiply results and a plurality of third register values packed into a third register.    
     
     
         8 . The memory of  claim 7  further comprising an OPcode instruction for setting a mask indicating which partitioned fields of at least one of said registers are to be operated on.  
     
     
         9 . A microprocessor for performing both graphics and non-graphics operations, comprising: 
 a source register; and    divide and square-root logic having an input coupled to said source register and being configured to determine the value of one divided by the square root of each of a plurality of values in said source register in parallel.    
     
     
         10 . The microprocessor of  claim 9  wherein said divide and square-root logic comprises a look-up table.  
     
     
         11 . The microprocessor of  claim 9  wherein said divide and square-root logic comprises iterative logic.  
     
     
         12 . A computer readable memory accessible by a microprocessor for performing both graphics and non-graphics operations, comprising: 
 an OPcode instruction configured to cause said microprocessor to perform a determination of the value of one divided by the square-root of each of a plurality of partitioned fields of an input source register in parallel.    
     
     
         13 . A microprocessor for performing both graphics and non-graphics operations, comprising: 
 a source register having a plurality of partitioned fields;    a destination register;    a mask register;    logic, coupled between said source and destination register, configured to, responsive to an extraction instruction, store selected ones of said partitioned fields from said source register into said destination register, said selected ones being determined by said mask register.    
     
     
         14 . The microprocessor of  claim 13  wherein said logic is configured to store said selected ones of said fields in the least significant fields of said destination register.  
     
     
         15 . The microprocessor of  claim 13  wherein said logic is configured to store said selected ones of said fields over corresponding fields in said destination register to effect a merge of said source and destination register contents.  
     
     
         16 . A computer readable memory accessible by a microprocessor for performing both graphics and non-graphics operations, comprising: 
 a first instruction configured to cause said microprocessor to enter a designated value in a mask register; and    a second instruction configured to cause said microprocessor to store selected ones of partitioned fields from a source register into a destination register, said selected ones being determined by said mask register.    
     
     
         17 . The memory of  claim 16  wherein said selected ones of said fields are stored in the least significant fields of said destination register.  
     
     
         18 . The memory of  claim 16  wherein said selected ones of said fields are stored over corresponding fields in said destination register to effect a merge of said source and destination register contents.  
     
     
         19 . A microprocessor for performing both graphics and non-graphics operations, comprising: 
 a source register having a plurality of partitioned fields;    a destination register; and    detection logic, coupled to said source register, configured to determine a location of a designated type of leading digit or sequence of digits and to store a pointer to said leading digit in said destination register.    
     
     
         20 . The microprocessor of  claim 19  wherein said designated type of leading digit is a one.  
     
     
         21 . The microprocessor of  claim 19  wherein said designated type of leading digit is a zero.  
     
     
         22 . The microprocessor of  claim 19  wherein said detection logic includes a priority decoder.  
     
     
         23 . The microprocessor of  claim 19  wherein said detection logic includes a shift register.  
     
     
         24 . A computer readable memory accessible by a microprocessor for performing both graphics and non-graphics operations, comprising: 
 an instruction configured to cause said microprocessor to determine a location of a designated type of leading digit or sequence of digits in a source register and to store a pointer to said leading digit in a destination register.    
     
     
         25 . The memory of  claim 24  wherein said pointer is an offset from a least significant bit.  
     
     
         26 . A microprocessor for performing both graphics and non-graphics operations, comprising: 
 an integer register file;    a floating point and graphics register file; and    exchange logic for moving the contents of a register in said floating point and graphics register file to a register in said integer register file.    
     
     
         27 . A computer readable memory accessible by a microprocessor for performing both graphics and non-graphics operations, comprising: 
 an instruction configured to cause said microprocessor to move the contents of a register in a floating point and graphics register file to a register in a integer register file.    
     
     
         28 . A microprocessor for performing both graphics and non-graphics operations, comprising: 
 a source register having a plurality of partitioned fields;    shift logic, coupled to said source register, configured to shift bits in each of said partitioned fields without shifting into adjacent partitioned fields; and    a control register for storing at least one bit used in a shift operation.    
     
     
         29 . The microprocessor of  claim 28 , wherein said shift logic is configured to shift a bit from at least one of said partitioned fields into said control register.  
     
     
         30 . The microprocessor of  claim 28  wherein said control register comprises a mask register for determining which of said partitioned fields is to be shifted.  
     
     
         31 . The microprocessor of  claim 28  wherein said shift logic is configured to, responsive to a left shift instruction, cause bits to be left shifted with zeroes being added to the least significant bit locations.  
     
     
         32 . The microprocessor of  claim 28  wherein said shift logic is configured to, responsive to a right shift instruction, cause bits to be right shifted with a sign bit being copied to the most significant bit locations for each partitioned field.  
     
     
         33 . The microprocessor of  claim 28  wherein said shift logic is configured to, responsive to a right shift instruction, cause bits to be right shifted with zeroes being added to the most significant bit locations for each partitioned field.  
     
     
         34 . A computer readable memory accessible by a microprocessor for performing both graphics and non-graphics operations, comprising: 
 an instruction configured to cause said microprocessor to shift bits in each of a plurality of partitioned fields without shifting into adjacent partitioned fields, and for storing in a control register at least one bit used for said shift.    
     
     
         35 . The memory of  claim 34 , wherein said instruction is configured to shift a bit from at least one of said partitioned fields into said control register.  
     
     
         36 . The memory of  claim 34  further comprising an instruction for writing a mask to a mask register for determining which of said partitioned fields is to be shifted.  
     
     
         37 . A microprocessor for performing both graphics and non-graphics operations, comprising: 
 a source memory location;    a destination register;    a mask register; and    move logic, coupled to said register file and said mask register, configured to move to said destination register a selected group of said partitioned fields from said source register, the selected group being determined in accordance with said mask register.    
     
     
         38 . The microprocessor of  claim 37  further comprising execution logic configured to perform a designated operation on said selected group of partitioned fields.  
     
     
         39 . The microprocessor of  claim 37  wherein said source memory location is a source register.  
     
     
         40 . A computer readable memory accessible by a microprocessor for performing both graphics and non-graphics operations, comprising: 
 a first instruction configured to cause said microprocessor to enter a designated value in a mask register; and    a second instruction configured to cause said microprocessor to move to a destination register a selected group of partitioned fields from a source register, the selected group being determined in accordance with said mask register.    
     
     
         41 . A microprocessor for performing both graphics and non-graphics operations, comprising: 
 an address register;    an adder coupled to said address register;    a graphics data destination register;    control logic, coupled to said address register and said adder, configured to load into said destination register graphics data at an address in a memory pointed to by an address in said address register, and to modify said address register using said adder.    
     
     
         42 . The microprocessor of  claim 41  wherein said control logic is configured to increment or decrement said address register in accordance with a data size.  
     
     
         43 . A computer readable memory accessible by a microprocessor for performing both graphics and non-graphics operations, comprising: 
 an instruction configured to cause said microprocessor to load into a destination register graphics data at an address in a memory pointed to by an address in an address register, and to modify said address register using a data size.    
     
     
         44 . The memory of  claim 43  further comprising: 
 a second instruction configured to cause said microprocessor to enter said data size in a data size register.  
 
     
     
         45 . The microprocessor of  claim 1  further comprising rounding logic for rounding a result of said multiply and add operations, but not an intermediate result.  
     
     
         46 . The microprocessor of  claim 3  further comprising rounding logic for rounding a result of said multiply and subtract operations, but not an intermediate result.