US2002090789A1PendingUtilityA1

Semiconductor device and method for fabricating the same

Assignee: FUJITSU LTDPriority: Apr 28, 1998Filed: Mar 8, 2002Published: Jul 11, 2002
Est. expiryApr 28, 2018(expired)· nominal 20-yr term from priority
H10D 64/281H10D 62/854H10D 62/852H10D 62/824H10D 62/177H10D 10/821H10F 77/1248H10D 10/021
37
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Claims

Abstract

The semiconductor device comprises a collector layer 14 ; a base layer 16 of a carbon-doped Ga x In 1−x As y Sb 1−y layer having one surface connected to the collector layer 14 ; an emitter layer 18 connected the other surface of the base layer 16 ; a base contact layer 30 of a carbon-doped GaAsSb layer electrically connected to the base layer 16 ; and a base electrode 32 formed on the base contact layer 30 . The semiconductor device of such structure can have a much reduced base resistance R B , whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency f max . Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.

Claims

exact text as granted — not AI-modified
What is claimed is  
     
         1 . A semiconductor device comprising: 
 a collector layer;    a base layer of a carbon-doped Ga x In 1−x As y Sb 1−y  layer having one surface connected to the collector layer;    an emitter layer connected the other surface of the base layer;    a base contact layer of a carbon-doped GaAsSb layer electrically connected to the base layer; and    a base electrode formed on the base contact layer.    
     
     
         2 . A semiconductor device according to  claim 1 , wherein 
 the base contact layer is formed on said one surface or said the other surface of the base layer.    
     
     
         3 . A semiconductor device according to  claim 1 , wherein 
 the base contact layer is formed on a surface of the collector layer connected to the base layer and has a side surface connected to a side surface of the base layer.    
     
     
         4 . A semiconductor device according to  claim 1 , wherein 
 the base contact layer is formed on a surface of the emitter layer connected to the base layer and has a side surface connected to a side surface of the base layer.    
     
     
         5 . A semiconductor device according to  claim 1 , further comprising 
 a surface passivation layer for protecting the base contact layer formed on the surface of the base contact layer with the base electrode formed on.    
     
     
         6 . A semiconductor device according to  claim 1 , wherein 
 the base contact layer is formed of a carbon-doped GaInAsSb layer in place of said carbon-doped GaAsSb layer.    
     
     
         7 . A semiconductor device according to  claim 1 , wherein 
 an As composition y of the Ga x In 1−x As y Sb 1−y  is 1, so that the base layer is formed of a InGaAs layer.    
     
     
         8 . A semiconductor device according to  claim 6 , wherein 
 an As composition y of the Ga x In 1−x As y Sb 1−y  is 1, so that the base layer is formed of a InGaAs layer.    
     
     
         9 . A semiconductor device according to  claim 1 , wherein 
 an In composition x of the Ga x In 1−x As y Sb 1−y  is 0, so that the base layer is formed of a GaAsSb layer.    
     
     
         10 . A semiconductor device according to  claim 6 , wherein 
 an In composition x of the Ga x In 1−x As y Sb 1−y  is 0, so that the base layer is formed of a GaAsSb layer.    
     
     
         11 . A semiconductor device according to  claim 1 , wherein 
 a dopant concentration of the base contact layer is not less than 1×10 20  cm −3 .    
     
     
         12 . A semiconductor device according to  claim 6 , wherein 
 a dopant concentration of the base contact layer is not less than 1×10 20  cm −3 .    
     
     
         13 . A method for fabricating a semiconductor device comprising the steps of: 
 forming a first semiconductor layer on a semiconductor substrate;    forming a base layer of a carbon-doped Ga x In 1−x As y Sb 1−y  layer on the first semiconductor layer;    forming a second semiconductor layer on the base layer;    patterning the second semiconductor layer in a mesa-shape;    forming a base contact layer on the base layer exposed by patterning the second semiconductor layer; and    forming a base electrode on the base contact layer.    
     
     
         14 . A method for fabricating a semiconductor device according to  claim 13 , further comprising, after the step of patterning the second semiconductor layer, a step of removing the base contact layer in a exposed region which is exposed by patterning the second semiconductor layer, wherein 
 in the step of forming the base contact layer, the base contact layer having a side surface connected to the base layer is formed on the first semiconductor layer exposed by removing the base layer.    
     
     
         15 . A method for fabricating a semiconductor device according to  claim 13 , wherein 
 in the step of forming the base layer, the base layer of an InGaAs layer which corresponds to the Ga x In 1−x As y Sb 1−y  layer whose As composition y is 1, or a GaAsSb layer which corresponds to the Ga x In 1−x As y Sb 1−y  layer whose In composition X is 0 is formed.    
     
     
         16 . A method for fabricating a semiconductor device according to  claim 14 , wherein 
 in the step of forming the base layer, the base layer of an InGaAs layer which corresponds to the Ga x In 1−x As y Sb 1−y  layer whose As composition y is 1, or a GaAsSb layer which corresponds to the Ga x In 1−x As y Sb 1−y  layer whose In composition X is 0 is formed.    
     
     
         17 . A method for fabricating a semiconductor device according to  claim 13 , wherein 
 in the step of forming the base contact layer, the base contact layer is formed of a material which lattice-matches with a material forming the base layer.    
     
     
         18 . A method for fabricating a semiconductor device according to  claim 13 , wherein 
 in the step of forming the base contact layer, the base contact layer is formed of a carbon-doped GaAsSb layer or a carbon-doped GaInAsSb layer.    
     
     
         19 . A method for fabricating a semiconductor device according to  claim 14 , wherein 
 in the step of forming the base contact layer, the base contact layer is formed of a carbon-doped GaAsSb layer or a carbon-doped GaInAsSb layer.    
     
     
         20 . A method for fabricating a semiconductor device according to  claim 13 , further comprising, before the step of forming the base contact layer, a step of thermal-treating for eliminating hydrogen in the base layer.  
     
     
         21 . A method for fabricating a semiconductor device according to  claim 13 , further comprising, after the step of patterning the second semiconductor layer, 
 a step of forming a sidewall insulation film on a side wall of a mesa of the second semiconductor layer.    
     
     
         22 . A method for fabricating a semiconductor device according to  claim 14 , further comprising, after the step of patterning the second semiconductor layer, 
 a step of forming a sidewall insulation film on a side wall of a mesa of the second semiconductor layer.    
     
     
         23 . A method for fabricating a semiconductor device according to  claim 13 , further comprising, after the step of forming the base contact layer, 
 a step of forming a surface passivation layer on the base contact layer for protecting the base contact layer.    
     
     
         24 . A method for fabricating a semiconductor device according to  claim 14 , further comprising, after the step of forming the base contact layer, 
 a step of forming a surface passivation layer on the base contact layer for protecting the base contact layer.    
     
     
         25 . A method for fabricating a semiconductor device according to  claim 13 , wherein 
 the first semiconductor layer or the second semiconductor layer is an emitter layer of an InP layer.    
     
     
         26 . A method for fabricating a semiconductor device according to  claim 14 , wherein 
 the first semiconductor layer or the second semiconductor layer is an emitter layer of an InP layer.

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