Current mode logic gates for low-voltage high-speed applications

Abstract

A new family of current mode logic (CML) gates ( 14 ) which, in one embodiment includes OR/NOR and AND/NAND gates, as well as more complex logic functions. The circuit uses a complementary signal to drive the gate of a feedback transistor ( 19 ) which has the effect of pseudo differential operation. Although it uses only single-ended inputs (A, B), because of this feedback aspect, the circuit has many of the advantages of a differential circuit such as low-voltage operation, higher immunity to noise, and less sensitivity to parasitic elements.

What is claimed is:  
     
         1 . An apparatus, comprising: 
 a first transistor, a second transistor, and a third transistor, each transistor having a first electrode, a second electrode, and a third electrode;    a first resistor coupling a first reference voltage to a first output and to said first electrode of said third transistor;    a second resistor coupling said first reference voltage to a second output and to said first electrodes of said first, second transistors and to said second electrode of said third transistor;    a first input coupled to said second electrode of said first transistor;    a second input coupled to said second electrode of said second transistor; and a second reference voltage coupled to said third electrodes of said first, second and third transistors.    
     
     
         2 . The apparatus of  claim 1 , wherein said first, second and third transistors are MOS transistors.  
     
     
         3 . The apparatus of  claim 2 , wherein: said first electrodes of said first, second and third transistors are the drain leads of said transistors; said second electrodes of said first, second and third transistors are the gate leads of said transistors; and said third electrodes of said first, second and third transistors are the source leads of said transistors.  
     
     
         4 . The apparatus of  claim 1 , wherein said first, second and third transistors are bipolar transistors.  
     
     
         5 . The apparatus of  claim 4 , wherein: said first electrodes of said first, second and third transistors are the collector leads of said transistors; said second electrodes of said first, second and third transistors are the base leads of said transistors; and said third electrodes of said first, second and third transistors are the emitter leads of said transistors.  
     
     
         6 . The apparatus of  claim 1 , wherein said first reference voltage is V DD.    
     
     
         7 . The apparatus of  claim 1 , wherein said second reference voltage is V SS.    
     
     
         8 . The apparatus of  claim 6 , wherein VDD is 1.8 volts or less. 
 The apparatus of  claim 7 , wherein V SS  is at ground or negative potential.    
     
     
         9 . The apparatus of  claim 1 , wherein the voltage swing of a signal coupled to said first input is 400 to 800 mVolts.  
     
     
         10 . The apparatus of  claim 1 , wherein the voltage swing of a signal coupled to said second input is 400-800 mVolts.  
     
     
         11 . The apparatus of  claim 1 , wherein said first and second inputs are single ended inputs.  
     
     
         12 . The apparatus of  claim 1 , wherein said apparatus is a logic gate. 
 The apparatus of  claim 12 , wherein said logic gate is a current-mode logic gate.    
     
     
         13 . The apparatus of  claim 1 , further comprising a fourth transistor, a first electrode of said fourth transistor coupled to first electrodes of said first and second transistors and to a second electrode of said third transistor; a third input coupled to a second electrode of said fourth transistor, and a third electrode of said fourth transistor coupled to said third electrodes of said first, second, and third transistors.  
     
     
         14 . A prescaler circuit, comprising: 
 an input buffer coupling input signals to clock and inverted clock signal inputs of first, second and third flip-flops;    a first input of said first flip-flop coupled to a first output of said second flip-flop;    a second input of said first flip-flop coupled to a first output of said third flip-flop;    a first output of said first flip-flop coupled to a first input of said second flip-flop and to a first clock input of a fourth flip-flop;    a second output of said first flip-flop coupled to a second input of said second flip-flop and to a second clock input of said fourth flip-flop;    a second output of said second flip-flop coupled to a first input of said third flip-flop;    a first output of said fourth flip-flop coupled to a second input of said third flip-flop and to a first clock input of a fifth flip-flop;    a second output of said fourth flip-flop coupled to a second clock input of said fifth flip-flop;    a third input of said third flip-flop coupled to the output of a logic gate;    a first input of said logic gate coupled to receive a select signal;    a first output of said fifth flip-flop coupled to a first clock input of a sixth flip-flop and to a second input of said logic gate;    a second output of said fifth flip-flop coupled to a second clock input of said sixth flip-flop;    a third input of said logic gate coupled to a first output of said sixth flip-flop;    
     
     
         15 . The prescaler circuit of  claim 14 , further comprising an input buffer coupling said first and second inputs to said first and second clock inputs of said first, second and third flip-flops.  
     
     
         16 . The prescaler circuit of  claim 14 , wherein said first clock input is a non-inverted clock input and said second clock input is an inverted clock input.  
     
     
         17 . The prescaler circuit of  claim 14 , wherein: 
 said first output of said first flip-flop is a non inverted output and said second out put is an inverted output;    said first output of said second flip-flop is an inverted output and said second output is a non-inverted output; and    said first output of said third flip-flop is an inverted output and said second output is a non-inverted output.    said first output of said fourth flip-flop is an inverted output and said second output is a non-inverted output.    said first output of said fifth flip-flop is an inverted output and said second output is a non-inverted output.    said first output of said sixth flip-flop is an inverted output and said second output is a non-inverted output.    
     
     
         18 . A phase-lock-loop comprising: 
 a charge pump coupling a filter to a phase detector, said phase detector being further coupled to receive a clock signal; and    a voltage controlled oscillator coupling a prescaler and an output to said filter, said prescaler being further coupled to said phase detector, said prescaler comprising: 
 an input buffer coupling input signals to clock and inverted clock signal inputs of first, second and third flip-flops;  
 a first input of said first flip-flop coupled to a first output of said second flip-flop;  
 a second input of said first flip-flop coupled to a first output of said third flip-flop;  
 a first output of said first flip-flop coupled to a first input of said second flip-flop and to a first clock input of a fourth flip-flop;  
 a second output of said first flip-flop coupled to a second input of said second flip-flop and to a second clock input of said fourth flip-flop;  
 a second output of said second flip-flop coupled to a first input of said third flip-flop;  
 a first output of said fourth flip-flop coupled to a second input of said third flip-flop and to a first clock input of a fifth flip-flop;  
 a second output of said fourth flip-flop coupled to a second clock input of said fifth flip-flop;  
 a third input of said third flip-flop coupled to the output of a logic gate;  
 a first input of said logic gate coupled to receive a select signal;  
 a first output of said fifth flip-flop coupled to a first clock input of a sixth flip-flop and to a second input of said logic gate;  
 a second output of said fifth flip-flop coupled to a second clock input of said sixth flip-flop; and  
 a third input of said logic gate coupled to a first output of said sixth flip-flop;  
   
     
     
         19 . A portable telephonic system, comprising: 
 a duplex switch coupling an antenna to a receiver and to a transmitter;    a power supply coupled to said receiver;    a baseband coupling said power supply to said receiver, transmitter and to a keypad and a speaker; a microphone coupled to said baseband; and a phase-lock-loop coupling said receiver to said transmitter, said phase-lock-loop comprising: 
 a charge pump coupling a filter to a phase detector, said phase detector being further coupled to receive a clock signal; and  
 a voltage controlled oscillator coupling a prescaler and an output to said filter, said prescaler being further coupled to said phase detector;  
   
     
     
         20 . The portable telephonic system of  claim 19 , wherein said prescaler comprises: 
 an input buffer coupling input signals to clock and inverted clock signal inputs of first, second and third flip-flops;    a first input of said first flip-flop coupled to a first output of said second flip-flop;    a second input of said first flip-flop coupled to a first output of said third flip-flop;    a first output of said first flip-flop coupled to a first input of said second flip-flop and to a first clock input of a fourth flip-flop;    a second output of said first flip-flop coupled to a second input of said second flip-flop and to a second clock input of said fourth flip-flop;    a second output of said second flip-flop coupled to a first input of said third flip-flop;    a first output of said fourth flip-flop coupled to a second input of said third flip-flop and to a first clock input of a fifth flip-flop;    a second output of said fourth flip-flop coupled to a second clock input of said fifth flip-flop;    a third input of said third flip-flop coupled to the output of a logic gate;    a first input of said logic gate coupled to receive a select signal;    a first output of said fifth flip-flop coupled to a first clock input of a sixth flip-flop and to a second input of said logic gate;    a second output of said fifth flip-flop coupled to a second clock input of said sixth flip-flop;    a third input of said logic gate coupled to a first output of said sixth flip-flop;    
     
     
         21 . The portable telephonic system of  claim 19 , wherein said baseband is an analog/digital baseband.  
     
     
         22 . The portable telephonic system of  claim 19 , wherein said power supply comprises a battery pack coupled to a power supply/regulators.