Semiconductor memory device and method for manufacturing the same

Abstract

A technology of preventing the threshold voltage of the transistor of a cell region from increasing and the refresh characteristic of the transistor of the cell region from deteriorating, while maintaining the characteristic of the transistor of core circuit/peripheral circuit regions of a semiconductor memory device, is provided. A semiconductor memory device comprises a first transistor comprised of a first gate, a first gate insulating film, a first source region, and a first drain region formed in core circuit/peripheral circuit regions of a semiconductor memory device having a cell region and core circuit/peripheral circuit regions, a planarized interlayer dielectric film which covers the first transistor, and a second transistor formed in the cell region, including a second source region, a second drain region, a second gate having a height corresponding to the height of the interlayer dielectric film, and a second gate insulating film. The first transistor is formed using conventional manufacturing processes, the second transistor is formed by a damascene method, using the interlayer dielectric film as the basis of a reverse gate pattern.

What is claimed is:  
     
         1 . A semiconductor memory device comprising: 
 a semiconductor substrate having a cell region and a core circuit/peripheral circuit region;    a first transistor comprised of a first gate, a first gate insulating film, a first source region, and a first drain region formed in in the core circuit/peripheral circuit region;    a planarized interlayer dielectric film which covers the first transistor; and    a second transistor formed in the cell region, comprising a second source region, a second drain region, a second gate having a height corresponding to the height of the interlayer dielectric film, and a second gate insulating film.    
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the second gate is formed to be level with the interlayer dielectric film.  
     
     
         3 . The semiconductor memory device of  claim 1 , wherein the first transistor further comprises a first spacer formed on the side wall of the first gate, the second gate of the second transistor is convex, and the second transistor further comprises a second spacer formed on the side wall of the second gate.  
     
     
         4 . The semiconductor memory device of  claim 2 , wherein the first transistor further comprises a first spacer formed on the side wall of the first gate, the second gate of the second transistor is convex, and the second transistor further comprises a second spacer formed on the side wall of the second gate.  
     
     
         5 . The semiconductor memory device of  claim 3 , wherein the second spacer is a first insulating film formed of a material having a high etch selectivity with respect to the interlayer dielectric film when exposed to a predetermined etchant.  
     
     
         6 . The semiconductor memory device of  claim 4 , wherein the second spacer is formed of a material having a high etch selectivity with respect to the interlayer dielectric film when exposed to a predetermined etchant.  
     
     
         7 . The semiconductor memory device of  claim 5 , wherein the interlayer dielectric film is one selected from the group consisting of a silicon nitride film, a silicon oxide film, a phosphosilicate glass (PSG) film, a borosilicate glass (BSG) film, a borophosphosilicate glass (BPSG) film, a tetraethylorthosilicate glass (TEOS) film, an ozone-TEOS film, an undopedsilicate glass (USG) film, and a combination of the above films, and the first insulating film is one selected from the group consisting of the silicon nitride film, an aluminum oxide film, and a tantalum oxide film.  
     
     
         8 . The semiconductor memory device of  claim 1 , wherein the second gate is formed of a polysilicon layer and a refractory metal layer and further comprises a second insulating film formed of a material having high etch selectivity with respect to the interlayer dielectric film formed on the refractory metal layer when exposed to a predetermined etchant.  
     
     
         9 . The semiconductor memory device of  claim 2 , wherein the second gate is formed of a polysilicon layer and a refractory metal layer and further comprises a second insulating film formed of a material having high etch selectivity with respect to the interlayer dielectric film formed on the refractory metal layer when exposed to a predetermined etchant.  
     
     
         10 . The semiconductor memory device of  claim 1 , wherein the second gate comprises a polysilicon layer and a refractory metal silicide layer.  
     
     
         11 . The semiconductor memory device of  claim 1 , wherein the second gate comprises a polysilicon layer and a refractory metal layer.  
     
     
         12 . The semiconductor memory device of  claim 1 , wherein the second gate is formed of a polysilicon layer and a refractory metal silicide layer and further comprises a second insulating film formed of a material having a high selectivity with respect to the interlayer dielectric film formed on the refractory metal silicide layer when exposed to a predetermined etchant.  
     
     
         13 . The semiconductor memory device of  claim 2 , wherein the second gate is formed of a polysilicon layer and a refractory metal silicide layer and further comprises a second insulating film formed of a material having a high etch selectivity with respect to the interlayer dielectric film formed on the refractory metal silicide layer when exposed to a predetermined etchant.  
     
     
         14 . The semiconductor memory device of  claim 12 , wherein the refractory metal silicide layer is one selected from the group consisting of CoSi X , TiSi X , TaSi X , MoSi X , WSi X , and PtSi X .  
     
     
         15 . The semiconductor memory device of  claim 12 , wherein the refractory metal silicide layer is one selected from the group consisting of CoSi X , TiSi X , TaSi X , MoSi X , WSi X , and PtSi X  and the second insulating film is one selected from the group consisting of a silicon nitride film, an aluminum oxide film, and a tantalum oxide film.  
     
     
         16 . The semiconductor memory device of  claim 12 , wherein the interlayer dielectric film is one selected from the group consisting of a silicon nitride film, a silicon oxide film, a PSG film, a BSG film, a BPSG film, a TEOS film, an ozone-TEOS film, a USG film, and a combination of the above films and the second insulating film is one selected from the group consisting of the silicon nitride film, an aluminum oxide film, and a tantalum oxide film.  
     
     
         17 . The semiconductor memory device of  claim 12 , wherein the first transistor further comprises a third insulating film formed on the top of the first gate and the second insulating film is thicker than the third insulating film.  
     
     
         18 . The semiconductor memory device of  claim 17 , wherein the thickness of the third insulating film is between 1500 and 2500 A.  
     
     
         19 . The semiconductor memory device of  claim 1 , further comprising a fourth insulating film, which is formed on the overall surface of the semiconductor substrate that belongs to the core circuit/peripheral circuit regions, in which the first transistor is formed, and has a high etch selectivity with respect to the interlayer dielectric film when exposed to a predetermined etchant.  
     
     
         20 . The semiconductor memory device of  claim 3 , further comprising a fourth insulating film, which is formed on the overall surface of the semiconductor substrate that belongs to the core circuit/peripheral circuit regions, in which the first transistor is formed, and has a high etch selectivity with respect to the interlayer dielectric film when exposed to a predetermined etchant.  
     
     
         21 . The semiconductor memory device of  claim 19 , further comprising a buffer film formed between the fourth insulating film and the semiconductor substrate in the core circuit/peripheral circuit regions.  
     
     
         22 . The semiconductor memory device of  claim 20 , wherein the interlayer dielectric film is one selected from the group consisting of a silicon nitride film, a silicon oxide film, a PSG film, a BSG film, a BPSG film, a TEOS film, an ozone-TEOS film, an USG film, and a combination of the above films and the fourth insulating film is one selected from the group consisting of the silicon nitride film, an aluminum oxide film, and a tantalum oxide film.  
     
     
         23 . The semiconductor memory device of  claim 21 , wherein the interlayer dielectric film is one selected from the group consisting of a silicon nitride film, a silicon oxide film, a PSG film, a BSG film, a BPSG film, a TEOS film, an ozone-TEOS film, an USG film, and a combination of the above films, the fourth insulating film is one selected from the group consisting of the silicon nitride film, an aluminum oxide film, and a tantalum oxide film, and the buffer film is one selected from the group consisting of the silicon oxide film and a silicon oxynitride film.  
     
     
         24 . The semiconductor memory device of  claim 1 , wherein the thickness of the second gate insulating film is equal to or greater than the thickness of the first gate insulating film.  
     
     
         25 . The semiconductor memory device of  claim 24 , wherein the first gate insulating film has a thickness of between  30  and  60 A.  
     
     
         26 . The semiconductor memory device of  claim 1 , wherein the second transistor further comprises an ion implantation region, which is formed in the semiconductor substrate under a second gate and into which impurity ions of the same conductive type of the semiconductor substrate are implanted.  
     
     
         27 . The semiconductor memory device of  claim 3 , wherein the second transistor further comprises an ion implantation region, which is formed in the semiconductor substrate corresponding to the second spacer and into which impurity ions of the same conductive type of the semiconductor substrate are implanted.  
     
     
         28 . A method for manufacturing a semiconductor memory device, comprising the steps of: 
 forming a semiconductor substrate having a cell region and at least one core circuit/peripheral circuit region;    forming a first transistor in the at least one core circuit/peripheral circuit region;    forming a planarized interlayer dielectric film covering the semiconductor substrate; and    forming a second transistor in the cell region by a damascene method, using reverse gate patterns defined on the interlayer dielectric film covering the cell region.    
     
     
         29 . The method of  claim 28 , wherein the step of forming the second transistor comprises the steps of: 
 forming reverse gate patterns by patterning the interlayer dielectric film positioned on the cell region and a first trench positioned between the reverse gate patterns;    forming a gate by filling the first trench with a conductive material;    forming a second trench by etching the reverse gate patterns; and    forming source and drain regions by implanting impurity ions using the gate as a mask.    
     
     
         30 . The method of  claim 29 , further comprising: 
 between the step of forming the first trench and the step of forming the gate, the step of forming a threshold voltage controlling impurity region in a predetermined portion of the semiconductor substrate by implanting impurity ions through the first trench.    
     
     
         31 . The method of  claim 30 , further comprising; 
 between the step of forming the first trench and-the step of forming the threshold voltage controlling impurity region, the step of forming spacers formed of a material having a high etch selectivity with respect to the interlayer dielectric film when exposed to a predetermined etchant on the outside walls of the reverse gate patterns.    
     
     
         32 . The method of  claim 31 , wherein the interlayer dielectric film is one selected from the group consisting of a silicon oxide film, a silicon nitride film, a PSG film, a BSG film, a BPSG film, a TEOS film, an ozone-TEOS film, a PE-TEOS film, a USG film, and a combination of the above films and the spacer is formed of a material different from the material that forms the interlayer dielectric film and is one selected from the group consisting of the silicon nitride film, an aluminum oxide film, and a tantalum oxide film.  
     
     
         33 . The method of  claim 28 , further comprising: 
 between the step of forming the first transistor and the step of forming the interlayer dielectric film, the step of forming an etching stop layer over the cell region and the at least one core circuit/peripheral circuit region, the etching stop layer formed of a material having a high etch selectivity with respect to the interlayer dielectric film when exposed to a predetermined etchant.    
     
     
         34 . The method of  claim 29 , further comprising the step of forming an etching stop layer formed of a material having a high etch selectivity with respect to the interlayer dielectric film under a predetermined etchant on the semiconductor substrate of the cell region and the core circuit/peripheral circuit regions, between the step of forming the first transistor and the step of forming the interlayer dielectric film.  
     
     
         35 . The method of  claim 33 , wherein the interlayer dielectric film is one selected from the group consisting of a silicon oxide film, a silicon nitride film, a PSG film, a BSG film, a BPSG film, a TEOS film, an ozone-TEOS film, a PE-TEOS film, a USG film, and a combination of the above films and the etching stop layer is formed of a material different from the material that forms the interlayer dielectric film and is one selected from the group consisting of the silicon nitride film, an aluminum oxide film, and a tantalum oxide film.  
     
     
         36 . The method of  claim 31 , further comprising: 
 between the step of forming the first transistor and the step of forming the first interlayer dielectric film, the step of forming an etching stop layer over the cell region and the at least one core circuit/peripheral circuit region, the etching stop layer formed of a material having a high etch selectivity with respect to the first interlayer dielectric film when exposed to a predetermined etchant.    
     
     
         37 . The method of  claim 36 , wherein the interlayer dielectric film is one selected from the group consisting of a silicon oxide film, a silicon nitride film, a PSG film, a BSG film, a BPSG film, a TEOS film, an ozone-TEOS film, a PE-TEOS film, a USG film, and a combination of the above films and the etching stop layer is formed of a material different from the material that forms the interlayer dielectric film and is one selected from the group consisting of the silicon nitride film, an aluminum oxide film, and a tantalum oxide film.  
     
     
         38 . The method of  claim 29 , wherein the step of forming the gate comprises the steps of: 
 forming a polysilicon layer, with which the first trench is filled to a first height;    forming a refractory metal layer, with which the trench is filled from the first height to a second height, and;    further comprising the step of forming an insulating film, with which the first trench is filled from the second height to the top of the first trench and which is formed of a material having a high etch selectivity with respect to the interlayer dielectric film when exposed to a predetermined etchant.    
     
     
         39 . The method of  claim 29 , wherein the step of forming the gate comprises the steps of: 
 forming a polysilicon layer, with which the first trench is filled to a first height;    forming a first refractory metal layer, with which the trench is filled from the first height to a second height;    changing some of the first refractory metal layer into a refractory metal silicide layer by silicide reaction, and    further comprising the step of forming an insulating film, with which the first trench is filled from the second height to the top of the first trench and which is formed of a material having a high etch selectivity with respect to the interlayer dielectric film when exposed to a predetermined etchant on the first refractory metal layer, some of which is changed into the refractory metal silicide layer.    
     
     
         40 . The method of  claim 29 , wherein the step of forming the gate comprises the steps of: 
 forming a polysilicon layer, with which the first trench is filled to a first height;    forming a first refractory metal layer, with which the trench is filled from the first height to a second height;    changing all of the first refractory metal layer into a refractory metal silicide layer by silicide reaction, and;    comprising the step of forming an insulating film, with which the first trench is filled from the second height to the top of the first trench and which is formed of a material having a high etch selectivity with respect to the interlayer dielectric film when exposed to a predetermined etchant on the refractory metal silicide layer.    
     
     
         41 . The method of  claim 38 , wherein the refractory metal layer is one selected from the group consisting of Co, W, Ta, Mo, and Ti, the interlayer dielectric film is one selected from the group consisting of a silicon oxide film, a silicon nitride film, a PSG film, a BSG film, a BPSG film, a TEOS film, an ozone-TEOS film, a PE-TEOS film, a USG film, and a combination of the above films, and the insulating film is formed of a material different from the material that forms the interlayer dielectric film and is one selected from the group consisting of the silicon nitride film, an aluminum oxide film, and a tantalum oxide film.  
     
     
         42 . The method of  claim 39 , wherein the first refractory metal layer is one selected from the group consisting of Co, W, Ta, Mo, and Ti, the refractory metal silicide layer is one selected from the group consisting of CoSi X , TiSi X , TaSi X , MoSi X , WSi X , and PtSi X , the interlayer dielectric film is one selected from the group consisting of a silicon oxide film, a silicon nitride film, a PSG film, a BSG film, a BPSG film, a TEOS film, an ozone-TEOS film, a PE-TEOS film, a USG film, and a combination of the above films, and the insulating film is formed of a material different from the material that forms the interlayer dielectric film and is one selected from the group consisting of the silicon nitride film, an aluminum oxide film, and a tantalum oxide film.  
     
     
         43 . The method of  claim 40 , wherein the first refractory metal layer is one selected from the group consisting of Co, W, Ta, Mo, and Ti, the refractory metal silicide layer is one selected from the group consisting of CoSi X , TiSi X , TaSi X , MoSi X , WSi X , and PtSi X , the interlayer dielectric film is one selected from the group consisting of a silicon oxide film, a silicon nitride film, a BSG film, a BPSG film, a TEOS film, an ozone-TEOS film, a PE-TEOS film, a USG film, and a combination of the above films, and the insulating film is formed of a material different from the material that forms the interlayer dielectric film and is one selected from the group consisting of the silicon nitride film, an aluminum oxide film, and a tantalum oxide film.  
     
     
         44 . The method of  claim 33 , further comprising: 
 between the step of forming the first transistor and the step of forming the etching stop layer, the step of forming a buffer film on the semiconductor substrate of the cell region and the at least one core circuit/peripheral circuit region.    
     
     
         45 . The method of  claim 44 , wherein the buffer film is a silicon oxide film or a silicon oxinitride film.  
     
     
         46 . The method of  claim 30 , further comprising the step of forming a contact pad by filling the second trench with polysilicon after the step of forming source and drain regions using the gate as a mask.  
     
     
         47 . The method of  claim 46 , wherein the step of forming the contact pad comprises the steps of: 
 forming a polysilicon layer on the overall surface of the semiconductor substrate that belongs to the cell region, in which the second trench is formed; and    etching the polysilicon layer until the upper surface of the gate is exposed.    
     
     
         48 . A semiconductor memory device, comprising: 
 a substrate;    first elements, which are formed in a first portion of the substrate and have various specifications;    an interlayer dielectric film covering the substrate in which the first elements are formed; and    second elements, which are formed in a second portion of the substrate, have a height corresponding to the interlayer dielectric film, and have a uniform specification.    
     
     
         49 . A method for manufacturing a semiconductor memory device, comprising the steps of: 
 forming first elements having various specifications in the second region of a semiconductor memory device having first and second regions;    forming a planarized interlayer dielectric film on the overall surfaces of the first and second regions in which the first elements are formed; and    forming second devices having a uniform specification in the second region by a damascene method, using the interlayer dielectric film positioned in the second region as the basis of a reverse gate pattern.