Thin layer semi-conductor structure comprising a heat distribution layer

Abstract

The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer ( 2 ) separated from a support substrate ( 1 ) by an intermediate zone ( 3 ), the intermediate zone ( 3 ) being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate. The intermediate zone has a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and includes at least one first layer, of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer ( 2 ), the intermediate zone including additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.

1 . A thin layer semi-conductor structure including a semi-conductor surface layer ( 2 ,  12 ,  22 ) separated from a support substrate ( 1 ,  11 ,  21 ) by an intermediate zone ( 3 ,  13 ,  33 ), the intermediate zone ( 3 ,  13 ,  33 ) being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate, having a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and including at least one first layer, -of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer ( 2 ,  12 ,  22 ), characterised in that the intermediate zone includes additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.  
     
     
         2 . A semi-conductor structure according to  claim 1 , characterised in that the thickness of the first layer is selected as a function of the dimension of the zones of heat dissipation of the electronic devices.  
     
     
         3 . A semi-conductor structure according to  claim 1 , characterised in that the second layer is able to provide adhesion considered as satisfactory between the intermediate zone and the support substrate.  
     
     
         4 . A semi-conductor structure according to  claim 1 , characterised in that the intermediate zone ( 3 ,  13 ) includes a third, insulating, layer ( 5 ,  15 ) between the first layer and the semi-conductor surface layer ( 2 ,  12 ), said third layer conferring on the intermediate zone said electrical quality of interface.  
     
     
         5 . A semi-conductor structure according to  claim 4 , characterised in that, the semi-conductor structure being an SOI structure, the third layer ( 5 ,  15 ) is a layer of silicon oxide.  
     
     
         6 . A semi-conductor structure according to  claim 5 , characterised in that the third layer ( 5 ,  15 ) is a layer of silicon oxide obtained for example by thermal oxidation.  
     
     
         7 . A semi-conductor structure according to any one of  claims 1  to  6 , the structure being an SOI structure, characterised in that the second layer ( 6 ,  16 ) is a layer of silicon oxide.  
     
     
         8 . A semi-conductor structure according to any one of  claims 1  to  7 , characterised in that the first layer ( 4 ,  14 ) is constituted by a material chosen from among polycrystalline silicon, diamond, alumina, silicon nitride, aluminium nitride, boron nitride, silicon carbide.  
     
     
         9 . A semi-conductor structure according to  claim 1 , characterised in that the first layer ( 24 ) is in contact with the semi-conductor surface layer ( 22 ) and is able to confer said electrical quality of interface.  
     
     
         10 . A semi-conductor structure according to  claim 9 , characterised in that, the semi-conductor structure being an SOI structure, said first layer ( 24 ) is a layer of cubic silicon carbide.  
     
     
         11 . A semi-conductor structure according to any one of  claims 1  to  10 , characterised in that the second layer of the intermediate zone has sufficient thickness of insulant of low dielectric constant for the stray capacitance present between the semi-conductor surface layer ( 2 ,  12 ,  22 ) and the support substrate ( 1 ,  11 ,  21 ) to be sufficiently low to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer ( 2 ,  12 ,  22 ).  
     
     
         12 . A process for manufacturing a semi-conductor structure according to  claim 1 , characterised in that it includes the following stages: 
 manufacture of the layers of the intermediate zone on one face of a first substrate intended to supply said semi-conductor surface layer and/or on one face of a second substrate intended to supply the support substrate of the structure,    bonding of the first substrate on the second substrate, said faces being placed opposite each other,    making of said semi-conductor surface layer.    
     
     
         13 . A process according to  claim 12 , characterised in that making said semi-conductor surface layer includes reducing the thickness of the first substrate.  
     
     
         14 . A process according to one of the claims  12  or  13 , characterised in that bonding the first substrate onto the second substrate is achieved by molecular adhesion.  
     
     
         15 . A process according to  claim 14 , characterised in that the manufacturing stage of the layers of the intermediate zone includes the deposition of at least one bonding layer to allow bonding by molecular adhesion.  
     
     
         16 . A process according to  claim 15 , characterised in that said bonding layer is a silicon oxide layer.  
     
     
         17 . A process according to any one of  claims 12  to  16 , characterised in that the first layer is a layer of a material chosen from among polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, alumina deposited by reactive cathode sputtering, silicon nitride deposited by CVD, aluminium nitride deposited by CVD, boron nitride deposited by CVD and silicon carbide deposited by CVD.  
     
     
         18 . A process according to any one of  claims 13  to  17 , characterised in that the reduction in the thickness of the first substrate ( 10 ) is obtained by using one or more technologies from among: rectification, chemical etching, polishing, separation following thermal treatment along a cleavage plane induced by ion implantation.