Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices

Abstract

A multi-layer integrated circuit ( 400 ) and method of manufacturing thereof having barbed vias ( 427 ) connecting conductive lines ( 468, 408 ). Circuit ( 400 ) includes a first dielectric layer ( 404 ) deposited on a substrate ( 402 ) and conductive lines ( 408 ) formed in the first dielectric layer ( 404 ). A second dielectric layer ( 462 ) is deposited over the first dielectric layer ( 404 ). Barbed vias ( 427 ) are formed having a substantially cylindrical portion ( 424 ) within the second dielectric layer ( 462 ) and a barbed portion ( 426 ) within conductive lines ( 408 ). Conductive lines ( 468 ) are formed over the barbed vias ( 427 ) within a the second dielectric layer ( 462 ). A region of the barbed via ( 427 ) barbed portion ( 406 ) extends beneath the second dielectric layer ( 462 ).

what is claimed is:  
     
         1 . A method of interconnecting conductive layers in a multi-layer integrated circuit, wherein the method comprises: 
 depositing a dielectric layer over a first conductive region;    forming a via opening over at least a portion of the first conductive region in the dielectric layer;    forming a barb opening in a top portion of the first conductive region, the barb opening having a region extending beneath the dielectric layer; and    filling the via opening and the barb opening with a conductive material to form a barbed via.    
     
     
         2 . The method according to  claim 1  wherein depositing a dielectric layer comprises depositing a low-dielectric constant material.  
     
     
         3 . The method according to  claim 1  wherein depositing a dielectric layer comprises depositing a material having a dielectric constant of 3.6 or less.  
     
     
         4 . The method according to  claim 1  wherein filling the via opening and the barb opening comprises: 
 depositing a conformal conductive liner on the via and barb openings;  
 depositing a conformal seed layer over the conformal conductive liner; and  
 depositing a metal fill layer over the conformal seed layer.  
 
     
     
         5 . The method according to  claim 4  wherein depositing a metal fill layer comprises electroplating a metal.  
     
     
         6 . The method according to  claim 1  wherein the barbed via comprises copper.  
     
     
         7 . The method according to  claim 1  wherein forming a via opening comprises exposing the dielectric layer to an anisotropic etch.  
     
     
         8 . The method according to  claim 1  wherein forming a barb opening comprises exposing the top portion of the first conductive region to an isotropic etch.  
     
     
         9 . The method according to  claim 1  wherein forming a barb opening comprises forming an opening having a region extending beneath the second dielectric layer near at least approximately one-half of the via opening diameter.  
     
     
         10 . The method according to  claim 9  wherein forming a barb opening in a top portion of the first conductive line comprises forming an opening having a region extending beneath the second dielectric layer near approximately the entire via opening diameter.  
     
     
         11 . A method of manufacturing interconnect layers of a multi-layer integrated circuit, comprising: 
 forming a first conductive region in a first dielectric layer;    depositing a second dielectric layer over the first conductive region and the first dielectric layer, the second dielectric layer comprising a low-dielectric constant material;    forming a via opening over the first conductive region in the second dielectric layer; and    forming a barb opening in a top portion of the first dielectric region, the barb opening having a region extending beneath the second dielectric layer.    
     
     
         12 . The method according to  claim 11 , further comprising: 
 filling the via opening and the barb opening with a conductive material to form a barbed via;    depositing a third dielectric layer over the barbed via and the second dielectric layer; and    forming a second conductive region in the third dielectric layer over the barbed via.    
     
     
         13 . The method according to  claim 11 , further comprising: 
 forming a trench for a second conductive region in the third dielectric layer over the barbed via; and    filling the via opening, the barb opening and the second conductive region with a conductive material to form a barbed via and a second conductive region.    
     
     
         14 . The method according to  claim 11  wherein filling the via opening and the barb opening comprises: 
 depositing a conformal conductive liner on the via and barb openings;  
 depositing a conformal seed layer over the conformal conductive liner; and  
 depositing a metal fill layer over the conformal seed layer.  
 
     
     
         15 . The method according to  claim 14  wherein depositing a metal fill layer comprises electroplating a metal.  
     
     
         16 . The method according to  claim 11  wherein the first conductive region, second conductive region and barbed via comprise copper.  
     
     
         17 . The method according to  claim 11  wherein forming the via opening comprises exposing the second dielectric layer to an anisotropic etch.  
     
     
         18 . The method according to  claim 11  wherein forming a barb opening comprises exposing the top portion of the first conductive region to an isotropic etch.  
     
     
         19 . The method according to  claim 11  wherein forming a barb opening in a top portion of the first conductive region comprises forming an opening having a region extending beneath the second dielectric layer near at least approximately one-half of the via opening diameter.  
     
     
         20 . The method according to  claim 19  wherein forming a barb opening in a top portion of the first conductive region comprises forming an opening having a region extending beneath the second dielectric layer near approximately the entire via opening diameter.  
     
     
         21 . An interconnect structure for a multi-layer integrated circuit, comprising: 
 a first conductive region;    a dielectric layer disposed over the first conductive region;    a barbed via formed in the second dielectric layer over at least a portion of the first conductive region, the barbed via having a barbed portion extending into a top portion of the first conductive region, the barbed portion having a portion extending beneath the dielectric layer; and    a second conductive region formed above the barbed via.    
     
     
         22 . The structure according to  claim 21  wherein the second dielectric layer comprises a low-dielectric constant material.  
     
     
         23 . The structure according to  claim 21  wherein the second dielectric layer comprises a material having a dielectric constant of 3.6 or less.  
     
     
         24 . The structure according to  claim 21  wherein the barbed via comprises: 
 a conformal conductive liner deposited on the dielectric layer and the first conductive region top portion;  
 a conformal seed layer deposited on the conformal conductive liner; and  
 a metal fill layer deposited on the conformal seed layer.  
 
     
     
         25 . The structure according to  claim 21  wherein the first conductive region, second conductive region and barbed via comprise copper.  
     
     
         26 . The structure according to  claim 21  wherein the barbed via comprises a barbed portion and a cylindrical portion, wherein the barbed portion extends beneath the second dielectric layer near at least approximately one-half of the via cylindrical portion diameter.  
     
     
         27 . The structure according to  claim 21  wherein the barbed via barbed portion extends beneath the second dielectric layer near approximately the entire via cylindrical portion diameter.  
     
     
         28 . The structure according to  claim 21  further comprising: 
 a second dielectric layer disposed beneath the dielectric layer around the first conductive region.  
 
     
     
         29 . The structure according to  claim 28  further comprising: 
 a third dielectric layer disposed over the dielectric layer around the second conductive region.