Clock signal generation apparatus

Abstract

A clock signal generation apparatus includes a first device for extracting reference information from an input digital signal. An oscillator operates for generating a reference clock signal having a frequency depending on a control signal. A second device connected to the first device and the oscillator operates for generating the control signal to the oscillator in response to the reference clock signal generated by the oscillator and the reference information extracted by the first device, and for locking a phase of the reference clock signal to the reference information. A third device connected to the second device operates for deciding whether or not the phase of the reference clock signal is successfully locked to the reference information. A fourth device connected to the second device, a memory, and the third device operates for storing the control signal generated by the second device into the memory when the third device decides that the phase of the reference clock signal is successfully locked to the reference information. A fifth device connected to the memory, the oscillator, and the second device operates for selecting one of the control signal currently generated by the second device and the control signal stored in the memory, and for feeding the selected control signal to the oscillator.

What is claimed is:  
     
         1 . A clock signal generation apparatus comprising: 
 first means for extracting reference information from an input digital signal;    an oscillator for generating a reference clock signal having a frequency depending on a control signal;    second means connected to the first means and the oscillator for generating the control signal to the oscillator in response to the reference clock signal generated by the oscillator and the reference information extracted by the first means, and for locking a phase of the reference clock signal to the reference information;    a memory;    third means connected to the second means for deciding whether or not the phase of the reference clock signal is successfully locked to the reference information;    fourth means connected to the second means, the memory, and the third means for storing the control signal generated by the second means into the memory when the third means decides that the phase of the reference clock signal is successfully locked to the reference information; and    fifth means connected to the memory, the oscillator, and the second means for selecting one of the control signal currently generated by the second means and the control signal stored in the memory, and for feeding the selected control signal to the oscillator.    
     
     
         2 . A clock signal generation apparatus as recited in  claim 1 , wherein the fifth means comprises means for feeding the control signal currently generated by the second means to the oscillator when the input signal is equal to a received digital broadcasting signal, and means for feeding the stored control signal from the memory to the oscillator when the input signal is different from a received digital broadcasting signal.  
     
     
         3 . A clock signal generation apparatus as recited in  claim 1 , further comprising sixth means connected to the fourth means for inhibiting the fourth means from storing the control signal generated by the second means into the memory when an accuracy of the reference information is lower than a given accuracy.  
     
     
         4 . A clock signal generation apparatus comprising: 
 first means for extracting reference information from an input digital signal;    a first oscillator for generating a reference clock signal having a frequency depending on a control signal;    second means connected to the first means and the oscillator for generating a first error signal in response to the reference clock signal generated by the first oscillator and the reference information extracted by the first means;    a second oscillator for generating a basic signal having a fixed frequency;    third means connected to the first oscillator and the second oscillator for generating a second error signal in response to the reference clock signal generated by the first oscillator and the basic signal generated by the second oscillator; and    fourth means connected to the oscillator, the second means, and the third means for selecting one of the first error signal generated by the second means and the second error signal generated by the third means, and for feeding the selected error signal to the oscillator as the control signal;    wherein the reference clock signal is phase-locked to the reference information when the fourth means feeds the first error signal to the oscillator as the control signal, and the reference clock signal is phase-locked to the basic signal when the fourth means feeds the second error signal to the oscillator as the control signal.