Semiconductor integrated circuit device

Abstract

A semiconductor IC device includes, in a substrate, a P-type well region having a dynamic memory array section and applied with a reduced back bias voltage suitable for refreshing. Also included is a P-well region where N-channel MOSFETs of a peripheral circuit are formed. This P-well region is applied with a back bias voltage of an absolute value smaller than that applied to the P-type well of the memory array section. A P-type well section, where there are formed N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is applied with a back bias voltage of an absolute value large enough to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 an input terminal receiving an external voltage; and    a voltage formation circuit forming an internal voltage based on said external voltage,    wherein said internal voltage has a first change rate in response to a change of said external voltage, when said external voltage is in a first voltage range,    wherein said internal voltage has a second change rate in response to the change of said external voltage, when said external voltage is in a second voltage range, said second change rate being different from said first change rate,    wherein said internal voltage has a third change rate in response to the change of said external voltage, when said external voltage is in a third voltage range, said third change rate being different from said second change rate,    wherein said second voltage range is larger than said first voltage range, and    wherein said third voltage range is larger than said second voltage range.    
     
     
         2 . A semiconductor device according to  claim 1 , 
 wherein said first voltage range and said second voltage range are in series, and    wherein said second voltage range and said third voltage range are in series.    
     
     
         3 . A semiconductor device according to  claim 1 , 
 wherein said external voltage of said second voltage range is applied in a normal operation of said semiconductor device, and    wherein said external voltage of said third voltage range is applied in a test operation of said semiconductor device.    
     
     
         4 . A semiconductor device according to  claim 3 , 
 wherein said test operation is a burn-in test operation.    
     
     
         5 . A semiconductor device according to  claim 1 , 
 wherein said second change rate is substantially 0.    
     
     
         6 . A semiconductor device according to  claim 1 , 
 wherein said first change rate is different from said third change rate.    
     
     
         7 . A semiconductor device according to  claim 1 , 
 wherein said first change rate is the same as said third change rate.    
     
     
         8 . A semiconductor device according to  claim 1 , 
 wherein said internal voltage is applied to a P type well region of a semiconductor substrate of said semiconductor device.    
     
     
         9 . A semiconductor device comprising: 
 an input terminal receiving an external voltage; and    a voltage generation circuit generating an internal voltage based on said external voltage, said internal voltage being a negative voltage,    wherein the absolute value of a change of said internal voltage in response to a change of said external voltage is a first value, when said external voltage is in a first voltage range,    wherein the absolute value of the change of said internal voltage in response to the change of said external voltage is a second value, when said external voltage is in a second voltage range, said second value being smaller than said first value,    wherein the absolute value of the change of said internal voltage in response to the change of said external voltage is a third value, when said external voltage is in a third voltage range, said third value being larger than said second value,    wherein said second voltage range is larger than said first voltage range, and    wherein said third voltage range is larger than said second voltage range.    
     
     
         10 . A semiconductor device according to  claim 9 , 
 wherein said first voltage range and said second voltage range are in series, and    wherein said second voltage range and said third voltage range are in series.    
     
     
         11 . A semiconductor device according to  claim 9 , 
 wherein said external voltage of said second voltage range is applied in a normal operation of said semiconductor device, and    wherein said external voltage of said third voltage range is applied in a test operation of said semiconductor device.    
     
     
         12 . A semiconductor device according to  claim 11 , wherein 
 said test operation is a burn-in test operation.    
     
     
         13 . A semiconductor device according to  claim 9 , 
 wherein said second value is substantially 0.    
     
     
         14 . A semiconductor device according to  claim 9 , 
 wherein said first change rate is different from said third change rate.    
     
     
         15 . A semiconductor device according to  claim 9 , 
 wherein said first change rate is the same as said third change rate.    
     
     
         16 . A semiconductor device according to  claim 9 , 
 wherein said internal voltage is applied to a P type well region of a semiconductor substrate of said semiconductor device.    
     
     
         17 . A semiconductor device comprising a voltage forming circuit receiving a first voltage and outputting a second voltage, 
 wherein said second voltage is a negative voltage,    wherein said second voltage is a stable voltage, when said semiconductor device is in a normal operation, and    wherein said second voltage changes in accordance with said first voltage, when said semiconductor device is in a test operation.    
     
     
         18 . A semiconductor device according to  claim 17 , wherein 
 said test operation is a burn-in test operation.    
     
     
         19 . A semiconductor device according to  claim 17 , wherein 
 said internal voltage is applied to a P type well region formed in a semiconductor substrate of said semiconductor device.    
     
     
         20 . A semiconductor device comprising: 
 an input terminal receiving an external voltage; and    a voltage generation circuit generating an internal voltage in accordance with said external voltage, said internal voltage being a negative voltage,    wherein the absolute value of a change of said internal voltage in response to a change of said external voltage is a first value, when said external voltage is in a first voltage range,    wherein the absolute value of the change of said internal voltage to the change of said external voltage is a second value, when said external voltage is in a second voltage range, said second value being larger than said first value,    wherein said second voltage range is larger than said first voltage range, and    wherein said external voltage of said first voltage range is applied in a normal operation of said semiconductor device.    
     
     
         21 . A semiconductor device according to  claim 20 , wherein 
 said first voltage range and said second voltage range are in series.    
     
     
         22 . A semiconductor device according to  claim 20 , 
 wherein said external voltage of said second voltage range is applied in a test operation of said semiconductor device.    
     
     
         23 . A semiconductor device according to  claim 22 , 
 wherein said test operation is a burn-in test operation.    
     
     
         24 . A semiconductor device according to  claim 20 , wherein 
 said first value is substantially 0.    
     
     
         25 . A semiconductor device according to  claim 20 , 
 wherein said internal voltage is applied to a P type well region formed in a semiconductor substrate of said semiconductor device.    
     
     
         26 . A semiconductor device according to  claim 25 , further comprising: 
 a plurality of memory cells each of which comprises an N-channel transistor having source and drain regions formed in said P type well region.