CMOS device and method of manufacturing the same

Abstract

A semiconductor substrate having a first conductivity type is first prepared. Then, a well region is formed in the substrate so as to have a second conductivity type opposite to the first conductivity type. Next, a first ion having the first conductivity type is implanted into the well region to form a region to be a first drain region having a first impurity density and into the substrate to form a region to be a first channel stopper region. Next, a second ion having the second conductivity type is implanted into the well to form a region to be a second channel stopper region and into the substrate to form a region to be a the second drain region having a second impurity density. Then, the respective ion implanted regions are thermally diffused to form the first drain region and the second channel stopper region in the well region and to form the second drain region and the first channel stopper region in the substrate. Next, a third drain region is formed in the first drain region so as to have the first conductivity type and a third impurity density higher than the first impurity density. And a fourth drain region is formed in the second drain region so as to have the second conductivity type and a fourth impurity density higher than the second impurity density.

What is claimed is:  
     
         1 . A CMOS device comprising: 
 a p-channel MOS transistor including a first p-type drain region provided with a first p-type impurity density;    a n-channel MOS transistor including a first n-type drain region provided with a first n-type impurity density;    a second p-type drain region formed in the first p-type drain region, and provided with a second p-type impurity density higher than the first p-type impurity density; and    a second n-type drain region formed in the first n-type drain region, and provided with a second n-type impurity density higher than the first n-type impurity density.    
     
     
         2 . A method of manufacturing a CMOS device comprising the steps of: 
 preparing a semiconductor substrate having a first conductivity type;    forming a well region in the substrate, the well having a second conductivity type opposite to the first conductivity type;    implanting a first ion having the first conductivity type, into the well region to form a region to be a first drain region having a first impurity density and into the substrate to form a region to be a first channel stopper region;    implanting a second ion having the second conductivity type, into the well to form a region to be a second channel stopper region and into the substrate to form a region to be a the second drain region having a second impurity density;    thermally diffusing the respective ion implanted regions to form the first drain region and the second channel stopper region in the well region and to form the second drain region and the first channel stopper region in the substrate;    forming a third drain region in the first drain region so as to have the first conductivity type and a third impurity density higher than the first impurity density; and    forming a fourth drain region in the second drain region so as to have the second conductivity type and a fourth impurity density higher than the second impurity density.    
     
     
         3 . The manufacturing method as set forth in  claim 2 , wherein the first conductivity type is n-type and the second conductivity type is p-type.  
     
     
         4 . The manufacturing method as set forth in  claim 2 , wherein the first conductivity type is p-type and the second conductivity type is n-type.