US2002070913A1PendingUtilityA1

Transistor circuit, display panel and electronic apparatus

Assignee: SEIKO EPSON CORPPriority: Mar 18, 1998Filed: Feb 8, 2002Published: Jun 13, 2002
Est. expiryMar 18, 2018(expired)· nominal 20-yr term from priority
H10W 20/0698G09G 3/3291G09G 2300/0861G09G 2300/0426G09G 2310/061G09G 3/006G09G 2300/0819G09G 2300/0465G09G 3/30G09G 2320/043G09G 2310/0251G09G 3/3233G09G 2300/0814G09G 2310/0264G09G 3/3266G09G 2330/021G09G 3/3258G09G 2320/0233G09G 2310/08
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Claims

Abstract

A transistor circuit ( 100 ) including a driving transistor ( 110 ) where conductance between a source and a drain is controlled in response to voltage, and a compensating transistor ( 120 ) where a gate is connected to one of a source and a drain and wherein the compensating transistor is connected so as to supply input signals to the gate of the driving transistor through the source and drain. In a transistor circuit where conductance control in a driving transistor is carried out in response to the voltage of input signals, it is possible to control the conductance by using input signals of a relatively low voltage and a variance in threshold characteristics of driving transistors is compensated. With this transistor circuit, a display panel that can display picture images with reduced uneven brightness is achieved.

Claims

exact text as granted — not AI-modified
1 . A transistor circuit comprising a driving transistor including a first gate, a first source and a first drain, wherein conductance between the first source and the first drain is controlled in response to a voltage of input signals supplied to the first gate; and a compensating transistor including a second gate, a second source and a second drain, wherein the second gate is connected to one of the second source and the second drain, and wherein the compensating transistor is connected to the first gate in an orientation so as to supply the input signals to the first gate through the second source and the second drain, and to permit the first gate to move electric charge into a direction to lower the conductance.  
     
     
         2 . The transistor circuit according to  claim 1 , further comprising a resetting means for supplying reset signals having a voltage that gives a level of conductance that is higher than a maximum level of the conductance controlled in response to the input signals to the first gate before the input signals are supplied.  
     
     
         3 . The transistor circuit according to  claim 2 , wherein the reset signals are set to a voltage higher than a maximum voltage of the input signals by a threshold voltage level of the compensating transistor.  
     
     
         4 . The transistor circuit according to  claim 2  or  claim 3 , wherein the resetting means comprises a resetting transistor including a third gate, a third source and a third drain, wherein one of the third source and third drain is connected to the first gate, and wherein the reset signals are supplied to the first gate through the third source and the third drain when reset timing signals are supplied to the third gate before the supply of the input signals.  
     
     
         5 . The transistor circuit according to any of claims  1 ,  2 ,  3  and  4 , wherein the driving transistor and the compensating transistor are a same type of transistors.  
     
     
         6 . The transistor circuit according to any of claims  1 ,  2 ,  3 ,  4  and  5 , further comprising a switching transistor that includes a fourth gate, a fourth source and a fourth drain, and that is connected so as to supply the input signals to the compensating transistor through the fourth source and the fourth drain when switching timing signals are supplied to the fourth gate.  
     
     
         7 . The transistor circuit according to any of claims  1 ,  2 ,  3 ,  4 ,  5  and  6 , further comprising a storage capacitor connected to the first gate.  
     
     
         8 . The transistor circuit according to any of claims  1 ,  2 ,  3 ,  4 ,  5 ,  6  and  7 , wherein the transistors are respectively thin-film transistors formed on a same substrate.  
     
     
         9 . The transistor circuit according to any of claims  1 ,  2 ,  3 ,  4 ,  5 ,  6  and  7 , wherein the transistors are respectively bipolar transistors wherein the gate, the source and the drain correspond to a base, an emitter and a collector respectively.  
     
     
         10 . The transistor circuit according to any of claims  1 ,  2 ,  3 ,  4 ,  5 ,  6 ,  7 ,  8  and  9 , wherein the input signals are voltage signals where a voltage is controlled by an input signal source, wherein the driving transistor has one of the first source and first drain connected to a current-controlled element and controls electric current flowing to the current-controlled element by controlling the conductance.  
     
     
         11 . A display panel comprising respectively the transistor circuits of  claim 10  and a plurality of picture elements arranged in a matrix, wherein current-controlled light-emitting elements are applied respectively to the plurality of picture elements as the current-controlled elements.  
     
     
         12 . An electronic apparatus, comprising the display panel of claim  11 .

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