High speed flip-flop

Abstract

A bistable device has first and second complementary input terminals and first and second bistable states that are determined by the polarity of the signal applied to one of the input terminals. A source of an uninverted binary input signal, preferably an uninverted data stream, has a first value or a second value. A source of an inverted binary input signal, preferably an inverted data stream, has a first value or a second value in complementary relationship to the values of the uninverted input signal. A first source of a trigger signal has one polarity. A second source of a trigger signal has the other polarity. The first trigger signal is applied to the first input terminal and the second trigger signal is applied to the second input terminal to drive the bistable device into the first stable state when the input signal has the first value. The first trigger signal is applied to the second input terminal and the second trigger signal is applied to the first input terminal to drive the bistable device into the second stable state when the input signal has the second value.

What is claimed is:  
     
         1 . A driving circuit for a bistable device comprising: 
 a bistable device that has first and second complementary input terminals and first and second bistable states that are determined by the polarity of the signal applied to one of the input terminals;    a source of an uninverted binary input signal that has a first value or a second value;    a source of an inverted binary input signal that has a first value or a second value in complementary relationship to the values of the uninverted input signal;    a first source of a trigger signal having one polarity;    a second source of a trigger signal having the other polarity;    means for applying the first source of a trigger signal to the first input terminal and the second source of a trigger signal to the second input terminal to drive the bistable device into the first stable state when the input signal has the first value; and    means for applying the first source of a trigger signal to the second input terminal and the second source of a trigger signal to the first input terminal to drive the bistable device into the second stable state when the input signal has the second value.    
     
     
         2 . The driving circuit of  claim 1 , in which the applying means comprises: 
 a first pair of complementary transistors each having an input terminal, an output terminal, and a control terminal;    a second pair of complementary transistors each having an input terminal, an output terminal, and a control terminal;    a connection between the output terminals of the first pair of transistors and the first input terminal of the bistable device;    a connection between the output terminals of the second pair of transistors and the second input terminal of the bistable device;    a connection between the source of an uninverted binary input signal and the control terminals of the first pair of transistors;    a connection between the source of an inverted binary input signal and the control terminals of the second pair of transistors;    a connection between the first source of a trigger signal and the input terminals of one transistor type of the first and second pairs to alternately couple the one polarity to the first and second input terminals of the bistable device;    and a connection between the second source of a trigger signal and the input terminals of the other transistor type of the first and second pairs to alternately couple the other polarity to the first and second input terminals of the bistable device in complementary relationship to the one polarity.    
     
     
         3 . A convertible latch comprising: 
 a bias supply having first and second terminals at different potentials;    a first switch having a control terminal, an output terminal, and a common terminal connected to the first terminal of the bias supply to bias the first switch for bistable operation;    a second switch having a control terminal connected to the control terminal of the first switch, an output terminal connected to the output terminal of the first switch, and a common terminal;    a third switch having a control terminal, an output terminal, and a common terminal connected to the first terminal of the bias supply to bias the third switch for bistable operation;    a fourth switch having a control terminal connected to the control terminal of the third switch, an output terminal connected to the output terminal of the third switch, and a common terminal connected to the second terminal of the bias supply to bias the fourth switch for bistable operation;    a first cross connection from the output terminals of the first and second switches to the control terminals of the third and fourth switches;    a second cross connection from the output terminals of the third and fourth switches to the control terminals of the first and second switches;    a test terminal;    a fifth switch having a control terminal connected to the test terminal, an output terminal connected to the common terminal of the second switch, and a common terminal connected to the second terminal of the bias supply to bias the second switch for bistable operation when the fifth switch is conductive and disable the second switch when the fifth switch is non-conductive; and    a sixth switch having a control terminal connected to the test terminal, an output terminal connected to the common terminal of the fourth switch, and a common terminal connected to the second terminal of the bias supply to bias the fourth switch for bistable operation when the sixth switch is conductive and disable the fourth switch when the sixth switch is non-conductive.    
     
     
         4 . The latch of  claim 3 , in which the first, and third switches are CMOS transistors of one type and the second, fourth, fifth, and sixth switches are CMOS transistors of a type complementary to the one type.  
     
     
         5 . The latch of  claim 4 , in which the gains of the transistors are such that the first and third switches alternately float and cut-off when the second and fourth switches are non-conductive.  
     
     
         6 . The latch of  claim 4 , in which the potentials of the bias supply are such that the first and third switches alternately saturate and cut-off when the second and fourth switches are non-conductive.  
     
     
         7 . The latch of  claim 3 , additionally comprising complementary input terminals connected respectively to the control terminals of the first and second switches and the control terminals of the third and fourth switches.  
     
     
         8 . The latch of  claim 7  additionally comprising complementary output terminals connected respectively to the output terminals of the first and second switches and the output terminals of the third and fourth switches.  
     
     
         9 . The latch of  claim 8 , additionally comprising a first clocking switch connected between one of the complementary input terminals and the control terminals of the first and second switches and a second clocking switch connected between the other of the complementary input terminals and the control terminals of the third and fourth switches.  
     
     
         10 . A convertible latch comprising: 
 a first bistable stage having an input and an output;    a second bistable stage having an input and an output;    cross coupled connections between the output of each of the first and second stages and the input of the other stage so the first and second stages are alternately cut off or float;    a third bistable stage having an input and an output;    a fourth bistable stage having an input and an output;    cross coupled connections between the output of each of the third and fourth stages and the input of the other stage so the third and fourth stages are alternately cut off or saturated;    means for conditionally connecting the first and third stages in parallel and connecting the second and fourth stages in parallel to form a static latch when the connection is in place and a dynamic latch when the connection is not is place.